公开(公告)号：US08644405B2

公开(公告)日：2014-02-04

申请号：US13549553

申请日：2012-07-16

Applicant: Raj Kumar Jain ,  Sim Hak Keong

Inventor： Raj Kumar Jain ,  Sim Hak Keong

IPC: H04L27/28 ,  H04L5/12

CPC classification number: H04L27/2628 ,  H04L27/2633

Abstract: A new protocol is proposed for transmission of data through lines such as telephone lines. The tones of a signal are grouped, and Trellis encoding is performed only of the members of a group. The computational cost of coding and decoding the data is reduced (compared to treating all the tones of a given direction equivalently), and the invention makes it possible to significantly reduce the computational and memory requirements of the encoder and decoder. Furthermore, Trellis decoding errors are not propagated between the groups.

Abstract translation: 提出了一种新的协议，用于通过诸如电话线的线路传输数据。 信号的音调被分组，并且仅对组的成员执行网格编码。 减少数据编码和解码的计算成本（与处理给定方向的所有音调相当），本发明可以显着降低编码器和解码器的计算和存储要求。 此外，网格解码错误不会在组之间传播。

公开(公告)号：US20130058430A1

公开(公告)日：2013-03-07

申请号：US13549553

申请日：2012-07-16

Applicant: Raj Kumar Jain ,  Sim Hak Keong

Inventor： Raj Kumar Jain ,  Sim Hak Keong

IPC: H04L27/00

CPC classification number: H04L27/2628 ,  H04L27/2633

Abstract: A new protocol is proposed for transmission of data through lines such as telephone lines. The tones of a signal are grouped, and Trellis encoding is performed only of the members of a group. The computational cost of coding and decoding the data is reduced (compared to treating all the tones of a given direction equivalently), and the invention makes it possible to significantly reduce the computational and memory requirements of the encoder and decoder. Furthermore, Trellis decoding errors are not propagated between the groups.

Abstract translation: 提出了一种新的协议，用于通过诸如电话线的线路传输数据。 信号的音调被分组，并且仅对组的成员执行网格编码。 减少数据编码和解码的计算成本（与处理给定方向的所有音调相当），本发明可以显着降低编码器和解码器的计算和存储要求。 此外，网格解码错误不会在组之间传播。

公开(公告)号：US08116362B2

公开(公告)日：2012-02-14

申请号：US11344955

申请日：2006-02-01

Applicant: Raj Kumar Jain ,  Hak Keong Sim

Inventor： Raj Kumar Jain ,  Hak Keong Sim

IPC: H04B1/38 ,  H04L5/16

CPC classification number: H04L27/2608 ,  H04L1/0071

Abstract: A line card is proposed in which one or more DMT processing modules 1 communicate with a data link layer platform, such as an ATM, POSPHY or Ethernet processor. The data relating to a single symbol is transmitted between the data link layer platform and a given one of DMT processing modules in a plurality of data portions spaced apart in time. The data portions relating to different channels of a given DMT processing module (or to different DMT processing modules) are interleaved in time. Since the data portions of a given symbol are spaced apart in time, the data relating to a single symbol is transmitted over a longer time period than in conventional devices which reduces the effective burstiness of the traffic, and thus reduces the memory requirements of the data link layer platform.

Abstract translation: 提出一种线卡，其中一个或多个DMT处理模块1与诸如ATM，POSPHY或以太网处理器之类的数据链路层平台进行通信。 与数据链路层平台和DMT处理模块中的给定的一个时间间隔的多个数据部分中传送与单个符号有关的数据。 与给定DMT处理模块（或不同的DMT处理模块）的不同信道有关的数据部分在时间上交错。 由于给定符号的数据部分在时间上是间隔开的，所以与传统设备相比，在单个符号上传输的数据比传统设备更长的时间间隔发送，这降低了业务的有效突发性，从而降低了数据的存储器要求 链路层平台。

公开(公告)号：US06704232B1

公开(公告)日：2004-03-09

申请号：US10065193

申请日：2002-09-25

Applicant: Raj Kumar Jain

Inventor： Raj Kumar Jain

IPC: G11C700

CPC classification number: G11C11/4091 ,  G11C7/1048 ,  G11C11/405

Abstract: An integrated memory device comprises a multitude of sense amplifiers which output an amplified data signal on a data line. The data line is forced to a precharge potential when idle. A transistor connects the data line to a precharge potential. The memory device avoids the kickback effect during a data read operation.

Abstract translation: 集成存储器件包括多个读出放大器，其在数据线上输出放大的数据信号。 空闲时，数据线被强制为预充电电位。 晶体管将数据线连接到预充电电位。 存储器件在数据读取操作期间避免了反冲效应。

公开(公告)号：US06487107B1

公开(公告)日：2002-11-26

申请号：US09855165

申请日：2001-05-14

Applicant: Raj Kumar Jain

Inventor： Raj Kumar Jain

IPC: G11C1140

CPC classification number: G11C11/405 ,  G11C11/403 ,  G11C11/404 ,  G11C11/406 ,  G11C11/4091 ,  H01L27/108 ,  H01L27/10873 ,  H01L27/11

Abstract: A memory cell having first and second access transistors coupled to a storage transistor is disclosed. During a write 0 operation, a degraded logic 0 is written into the memory cell. By storing a degraded logic 0, the leakage current is reduced.

Abstract translation: 公开了一种具有耦合到存储晶体管的第一和第二存取晶体管的存储单元。 在写0操作期间，将劣化逻辑0写入存储单元。 通过存储劣化的逻辑0，泄漏电流减小。

公开(公告)号：US07941604B2

公开(公告)日：2011-05-10

申请号：US11345645

申请日：2006-02-01

Applicant: Raj Kumar Jain ,  Xiao Ni Wei ,  Pin Xing Lin

Inventor： Raj Kumar Jain ,  Xiao Ni Wei ,  Pin Xing Lin

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F9/445 ,  G06F11/0724 ,  G06F11/0757

Abstract: A plurality of integrated circuits in a system, each having a program memory loaded with different sections of a program, and a second memory. The integrated circuits perform the program, such that, when one of the integrated circuits requires a portion of the program, which is contained in its own program memory, it extracts it from the program memory and uses it, but when it requires a portion of the program, which is not contained in its own program memory, it reads it from the program memory of one of the other integrated circuits into its second memory and runs that portion of the program from there. In one example, the system is a line card, and the program is specific to one DSL protocol.

Abstract translation: 一种系统中的多个集成电路，每个具有装载有程序的不同部分的程序存储器和第二存储器。 集成电路执行程序，使得当集成电路中的一个需要包含在其自己的程序存储器中的程序的一部分时，它从程序存储器中提取它并使用它，但是当它需要一部分 该程序不包含在其自己的程序存储器中，它将其从其他集成电路之一的程序存储器读取到其第二存储器中并从那里运行该程序的该部分。 在一个示例中，系统是线卡，并且该程序特定于一个DSL协议。

公开(公告)号：US07346746B2

公开(公告)日：2008-03-18

申请号：US10133941

申请日：2002-04-26

Applicant: Raj Kumar Jain ,  Rudi Frenzel

Inventor： Raj Kumar Jain ,  Rudi Frenzel

IPC: G06F12/08

CPC classification number: G06F12/0607 ,  G06F12/0888 ,  G06F2212/2532

Abstract: A system with multiple processors sharing a single memory module without noticeable performance degradation is described. The memory module is divided into n independently addressable banks, where n is at least 2 and mapped such that sequential addresses are rotated between the banks. A bank may be further divided into a plurality of blocks. A cache is provided to enable a processor to fetch from memory a plurality of data words from different memory banks to reduce memory latency caused by memory contention.

Abstract translation: 描述了具有共享单个存储器模块的多个处理器的系统，而没有明显的性能下降。 存储器模块被分成n个可独立寻址的存储体，其中n至少为2，并被映射使得顺序地址在存储体之间旋转。 银行可以进一步分为多个块。 提供缓存以使得处理器能够从存储器中获取来自不同存储体的多个数据字，以减少由存储器争用引起的存储器延迟。

公开(公告)号：US07209516B2

公开(公告)日：2007-04-24

申请号：US10161379

申请日：2002-06-03

Applicant: Raj Kumar Jain

Inventor： Raj Kumar Jain

IPC: H04B1/38 ,  H04J1/00

CPC classification number: H04L12/66

Abstract: An improved ADSL system with improved data rate is disclosed. In one embodiment, the upstream data bit rate is increased by extending the upstream transmission band. In another embodiment, the downstream data is also increased by extending the downstream transmission band.

Abstract translation: 公开了一种改进的数据速率的ADSL系统。 在一个实施例中，通过扩展上游传输频带来增加上游数据比特率。 在另一实施例中，下游数据也通过扩展下游传输频带而增加。

公开(公告)号：US06789150B1

公开(公告)日：2004-09-07

申请号：US09601581

申请日：2000-08-02

Applicant: Raj Kumar Jain

Inventor： Raj Kumar Jain

IPC: G06F1314

CPC classification number: G06F13/4022

Abstract: An integrated circuit (1) includes a processing device (2), a program interface (4, 5) coupled to the processing device (2), a data interface (6, 7) coupled to the processing device. The program interface (4, 5) includes a first address bus (4) and a first data bus (5) and the data interface (6, 7) includes a second address bus (6) and a second data bus (7). The integrated circuit also includes address and data bus switching devices (18) and a control device (16). The address bus switching device (18) is coupled to the first and second address buses (4, 6) and adapted to be coupled to an external address bus (11) and the data bus switching device (18) is adapted to be coupled to an external data bus (12) and is coupled to the first and second data buses (5, 7). The control device (16) is coupled to the processing device (2), the address bus switching device (18) and the data bus switching device (18). The control device (16) controls the address and data bus switching devices (18) to couple the first address bus (4) and the first data bus (5) to the external address and data buses (11, 12) or to couple the second address bus (6) and the second data bus (7) to the external address and data buses (11, 12), in response to control signals received from the processing device (2).

Abstract translation: 集成电路（1）包括处理设备（2），耦合到处理设备（2）的程序接口（4,5），耦合到处理设备的数据接口（6,7）。 程序接口（4,5）包括第一地址总线（4）和第一数据总线（5），数据接口（6,7）包括第二地址总线（6）和第二数据总线（7）。 集成电路还包括地址和数据总线切换装置（18）和控制装置（16）。 地址总线切换装置（18）耦合到第一和第二地址总线（4,6）并且适于耦合到外部地址总线（11），并且数据总线切换装置（18）适于耦合到 外部数据总线（12）并且耦合到第一和第二数据总线（5,7）。 控制装置（16）耦合到处理装置（2），地址总线切换装置（18）和数据总线切换装置（18）。 控制装置（16）控制地址和数据总线切换装置（18）将第一地址总线（4）和第一数据总线（5）耦合到外部地址和数据总线（11,12）或将 响应于从处理装置（2）接收的控制信号，将第二地址总线（6）和第二数据总线（7）连接到外部地址和数据总线（11,12）。

公开(公告)号：US06768668B2

公开(公告)日：2004-07-27

申请号：US10117665

申请日：2002-04-04

Applicant: Raj Kumar Jain

Inventor： Raj Kumar Jain

IPC: G11C1100

CPC classification number: G11C11/406 ,  G11C11/405 ,  G11C14/00

Abstract: The invention relates to a method for converting volatile memory cells to non-volatile memory cells with minimal modifications. There is included a volatile memory cell which is modified to permanently retain data by using one refresh port to transmit an active low voltage signal and configuring one terminal of the storage transistor to receive either an active high or low voltage signal.