公开(公告)号：US20220334981A1

公开(公告)日：2022-10-20

申请号：US17710578

申请日：2022-03-31

Applicant: Rambus Inc.

Inventor： Chi-Ming Yeung ,  Yoshie Nakabayashi ,  Thomas Giovannini ,  Henry Stracovsky

IPC: G06F13/16 ,  G11C5/02 ,  G11C5/04 ,  H03K19/1778 ,  G11C7/10

Abstract: System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).

公开(公告)号：US11768780B2

公开(公告)日：2023-09-26

申请号：US17710578

申请日：2022-03-31

Applicant: Rambus Inc.

Inventor： Chi-Ming Yeung ,  Yoshie Nakabayashi ,  Thomas Giovannini ,  Henry Stracovsky

IPC: G06F13/16 ,  G11C5/02 ,  G11C5/04 ,  H03K19/1778 ,  G11C7/10

CPC classification number: G06F13/16 ,  G11C5/02 ,  G11C5/04 ,  G11C7/10 ,  H03K19/1778

Abstract: System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).

公开(公告)号：US11537540B2

公开(公告)日：2022-12-27

申请号：US17316586

申请日：2021-05-10

Applicant: Rambus Inc.

Inventor： Chi-Ming Yeung ,  Yoshie Nakabayashi ,  Thomas Giovannini ,  Henry Stracovsky

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

公开(公告)号：US11294830B2

公开(公告)日：2022-04-05

申请号：US16837689

申请日：2020-04-01

Applicant: Rambus Inc.

Inventor： Chi-Ming Yeung ,  Yoshie Nakabayashi ,  Thomas Giovannini ,  Henry Stracovsky

IPC: G06F13/16 ,  G11C5/02 ,  G11C5/04 ,  H03K19/1778 ,  G11C7/10

Abstract: System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).

公开(公告)号：US12141081B2

公开(公告)日：2024-11-12

申请号：US18236272

申请日：2023-08-21

Applicant: Rambus Inc.

Inventor： Chi-Ming Yeung ,  Yoshie Nakabayashi ,  Thomas Giovannini ,  Henry Stracovsky

IPC: G06F13/16 ,  G11C5/02 ,  G11C5/04 ,  G11C7/10 ,  H03K19/1778

Abstract: System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).

公开(公告)号：US20240045813A1

公开(公告)日：2024-02-08

申请号：US18236272

申请日：2023-08-21

Applicant: Rambus Inc.

Inventor： Chi-Ming Yeung ,  Yoshie Nakabayashi ,  Thomas Giovannini ,  Henry Stracovsky

IPC: G06F13/16 ,  G11C5/02 ,  G11C5/04 ,  H03K19/1778 ,  G11C7/10

CPC classification number: G06F13/16 ,  G11C5/02 ,  G11C5/04 ,  H03K19/1778 ,  G11C7/10

Abstract: System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).

公开(公告)号：US11003601B2

公开(公告)日：2021-05-11

申请号：US16837844

申请日：2020-04-01

Applicant: Rambus Inc.

Inventor： Chi-Ming Yeung ,  Yoshie Nakabayashi ,  Thomas Giovannini ,  Henry Stracovsky

IPC: G06F13/20 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

公开(公告)号：US20250110897A1

公开(公告)日：2025-04-03

申请号：US18911111

申请日：2024-10-09

Applicant: Rambus Inc.

Inventor： Chi-Ming Yeung ,  Yoshie Nakabayashi ,  Thomas Giovannini ,  Henry Stracovsky

IPC: G06F13/16 ,  G11C5/02 ,  G11C5/04 ,  G11C7/10 ,  H03K19/1778

Abstract: System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).

公开(公告)号：US11907139B2

公开(公告)日：2024-02-20

申请号：US18085481

申请日：2022-12-20

Applicant: Rambus Inc.

Inventor： Chi-Ming Yeung ,  Yoshie Nakabayashi ,  Thomas Giovannini ,  Henry Stracovsky

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1673 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4282

Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

公开(公告)号：US10169258B2

公开(公告)日：2019-01-01

申请号：US15071072

申请日：2016-03-15

Applicant: Rambus Inc.

Inventor： Chi-Ming Yeung ,  Yoshie Nakabayashi ,  Thomas Giovannini ,  Henry Stracovsky

IPC: G06F13/20 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.