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公开(公告)号：US11671108B2
公开(公告)日：2023-06-06
申请号：US17728607
申请日：2022-04-25
Applicant: Rambus Inc.
Inventor： Kenneth C. Dyer , Marcus Van Ierssel
CPC classification number: H03M1/1023 , H03M1/0639 , H03M1/46
Abstract: Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are made until there is roughly an equal number of 1 and 0 values. This can reduce or eliminate the need for dedicated offset correction cycles.
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公开(公告)号：US11342929B2
公开(公告)日：2022-05-24
申请号：US17262901
申请日：2019-07-30
Applicant: Rambus Inc.
Inventor： Kenneth C. Dyer , Marcus Van Ierssel
Abstract: Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are made until there is roughly an equal number of 1 and 0 values. This can reduce or eliminate the need for dedicated offset correction cycles.
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公开(公告)号：US20180167080A1
公开(公告)日：2018-06-14
申请号：US15823355
申请日：2017-11-27
Applicant: Rambus Inc.
Inventor： Kenneth C. Dyer
CPC classification number: H03M1/1255 , H03M1/0624 , H03M1/0673 , H03M1/0836 , H03M1/1028 , H03M1/1057 , H03M1/1215
Abstract: An apparatus comprising M time-interleaved analog to digital converters (ADC) that sample an input signal at M sampling phases, wherein M is equal to or greater than 4. A phase control circuit adjusts at least M−1 sampling phases of the M sampling phases. The phase control circuit comprises M−1 phase error detector circuits. Each phase error detector circuit detects a corresponding phase error for a corresponding sampling phase of the M−1 sampling phases based on a sample captured at a sampling phase of the M sampling phases immediately preceding the corresponding sampling phase and a sample captured at a sampling phase of the M sampling phases immediately subsequent to the corresponding sampling phase.
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公开(公告)号：US20180167076A1
公开(公告)日：2018-06-14
申请号：US15818434
申请日：2017-11-20
Applicant: Rambus Inc.
Inventor： Masum Hossain , Kenneth C. Dyer , Nhat Nguyen , Shankar Tangirala
Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
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公开(公告)号：US12206423B2
公开(公告)日：2025-01-21
申请号：US18092564
申请日：2023-01-03
Applicant: Rambus Inc.
Inventor： Masum Hossain , Kenneth C. Dyer , Nhat Nguyen , Shankar Tangirala
Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
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Patent Agency Ranking
公开(公告)号：US11038514B2
公开(公告)日：2021-06-15
申请号：US16885805
申请日：2020-05-28
Applicant: Rambus Inc.
Inventor： Masum Hossain , Kenneth C. Dyer , Nhat Nguyen , Shankar Tangirala
Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
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公开(公告)号：US10523229B2
公开(公告)日：2019-12-31
申请号：US16227865
申请日：2018-12-20
Applicant: Rambus Inc.
Inventor： Kenneth C. Dyer
Abstract: An apparatus comprising M time-interleaved analog to digital converters (ADC) that sample an input signal at M sampling phases, wherein M is equal to or greater than 4. A phase control circuit adjusts at least M−1 sampling phases of the M sampling phases. The phase control circuit comprises M−1 phase error detector circuits. Each phase error detector circuit detects a corresponding phase error for a corresponding sampling phase of the M−1 sampling phases based on a sample captured at a sampling phase of the M sampling phases immediately preceding the corresponding sampling phase and a sample captured at a sampling phase of the M sampling phases immediately subsequent to the corresponding sampling phase.
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公开(公告)号：US20190238149A1
公开(公告)日：2019-08-01
申请号：US16227865
申请日：2018-12-20
Applicant: Rambus Inc.
Inventor： Kenneth C. Dyer
CPC classification number: H03M1/1255 , H03M1/06 , H03M1/0624 , H03M1/0673 , H03M1/08 , H03M1/0836 , H03M1/1028 , H03M1/1057 , H03M1/12 , H03M1/1215
Abstract: An apparatus comprising M time-interleaved analog to digital converters (ADC) that sample an input signal at M sampling phases, wherein M is equal to or greater than 4. A phase control circuit adjusts at least M−1 sampling phases of the M sampling phases. The phase control circuit comprises M−1 phase error detector circuits. Each phase error detector circuit detects a corresponding phase error for a corresponding sampling phase of the M−1 sampling phases based on a sample captured at a sampling phase of the M sampling phases immediately preceding the corresponding sampling phase and a sample captured at a sampling phase of the M sampling phases immediately subsequent to the corresponding sampling phase.
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公开(公告)号：US10230384B2
公开(公告)日：2019-03-12
申请号：US15818434
申请日：2017-11-20
Applicant: Rambus Inc.
Inventor： Masum Hossain , Kenneth C. Dyer , Nhat Nguyen , Shankar Tangirala
Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
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公开(公告)号：US10177778B2
公开(公告)日：2019-01-08
申请号：US15823355
申请日：2017-11-27
Applicant: Rambus Inc.
Inventor： Kenneth C. Dyer
Abstract: An apparatus comprising M time-interleaved analog to digital converters (ADC) that sample an input signal at M sampling phases, wherein M is equal to or greater than 4. A phase control circuit adjusts at least M−1 sampling phases of the M sampling phases. The phase control circuit comprises M−1 phase error detector circuits. Each phase error detector circuit detects a corresponding phase error for a corresponding sampling phase of the M−1 sampling phases based on a sample captured at a sampling phase of the M sampling phases immediately preceding the corresponding sampling phase and a sample captured at a sampling phase of the M sampling phases immediately subsequent to the corresponding sampling phase.
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