Abstract:
A modular feeder printing system is provided herein. It includes at least one, e.g., four, printing unit(s) and at least one, e.g., six, feeder module(s). An alignment means is incorporated at an end of each of the printing unit(s), such alignment means being adapted to be connected to an associated feeder module, preferably by means of a complementary alignment means which is incorporated at an end of each of the feeder module(s). The complementary alignment means is alignable and engageable with the alignment means. Latch means are cooperatively associated with the alignment means, in order to secure a selected printing unit to a selected feeder module. Finally, coupling means couple and synchronize drive power from the printing unit to the connected feeder module. By this module printing press, there is a substantial reduction in set-up time. This means that multiple printing press units can be configured in a suitable configuration to faciliate quality control of multiple presses by one operator at a central location. The standardization of settings on the feeder modules, when used with procedures for accurately positioning the printing image on the printing plates, further allows for almost instant registration of the image position on the printing sheet.
Abstract:
A method for forming a split gate flash cell memory device provides for establishing a floating gate region then using spacers or other hard mask materials that cover opposed edges of a gate electrode material in the gate region, to serve as hard masks during an etching operation that partially etches the gate electrode material which may be polysilicon. The gate electrode so produced serves as a floating gate electrode and includes a recessed central portion flanked by a pair of opposed upwardly extending fins which may terminate upwardly at an apex. A floating gate oxide is then formed by thermal oxidation and/or oxide deposition techniques.
Abstract:
A method and apparatus for combining video graphics processing and audio processing onto the same single chip and/or printed circuit board includes a graphics processing circuit, an audio processing circuit, a local bus, and a bus arbitrator. The local bus couples both the graphics processing circuit and audio processing circuit to the system bus such that each of the circuits may transceive data with the system bus. The bus arbitrator arbitrates access to the local bus between the graphics processing circuit and audio processing circuit. Such arbitration is based on incoming data, which is interpreted and, based on the interpretation, the bus arbitrator routes the incoming data to either the graphics processing circuit or the audio processing circuit. In addition, the bus arbitrator arbitrates outputting data from the graphics processing circuit and the audio processing circuit based on commands received from the CPU.
Abstract:
A method and apparatus for customized editing and/or censoring of video and/or audio signals begins when a signal and a plurality of editing parameters are received. The signal includes an audio and/or video signal, where each of the editing parameters corresponds to separate portions of the signal. The editing parameters may be embedded within the signal or provided in simulcast with the signal. While the signal is being processed, a selective editing circuit is monitoring the editing parameters. When an editing parameter indicates that the corresponding portion of the signal is to be edited, the selective editing circuit edits the corresponding portion based on the editing parameter, which may be provided by the content provider or the user. In addition, the editing parameter may indicate various levels of editing the signal. For example, the editing parameter may indicate that the portion of the audio and/or video signal is to be completely blanked, skipped, faded, distorted, or is to be replaced with a substitute audio and/or video signal.
Abstract:
A multiple pipeline memory controller has a plurality of two stage pipeline processors dedicated to separately process real time video capture and display refresh input request signals. A separate pipeline processor processes non-real time input signals. The multiple pipeline design reduces memory access latency and improves throughput of data in display FIFO memory to effect improved resolution. The multiple pipeline memory controller can be integrated in a video graphics controller (VGC).
Abstract:
A method for forming a split gate flash cell memory device provides for establishing a floating gate region then using spacers or other hard mask materials that cover opposed edges of a gate electrode material in the gate region, to serve as hard masks during an etching operation that partially etches the gate electrode material which may be polysilicon. The gate electrode so produced serves as a floating gate electrode and includes a recessed central portion flanked by a pair of opposed upwardly extending fins which may terminate upwardly at an apex. A floating gate oxide is then formed by thermal oxidation and/or oxide deposition techniques.
Abstract:
The present invention provides a personal propulsion device including a body unit having a center of gravity, where the body unit includes a thrust assembly providing a main conduit in fluid communication with at least two thrust nozzles, with the thrust nozzles being located above the center of gravity of the body unit. The thrust nozzles are independently pivotable about a transverse axis located above the center of gravity, and may be independently controlled by a single common linkage. The present invention may further include a base unit having an engine and a pump, which provides pressurized fluid to the body unit through a delivery conduit in fluid communication with both the base unit and the thrust assembly.
Abstract:
A display FIFO memory management system and method includes a programmable FIFO emulator for emulating a drain and fill time of the display FIFO memory to automatically predict a number of register entries remaining in the display FIFO memory at each predefined clock cycle. A programmable timer/counter has programmable precision to accommodate varying bandwidths of display screen display modes and is used to determine the number of entries remaining so that the emulator can accommodate varying screen display modes. A FIFO controller controls the timing of fetching display data from memory to fill the display FIFO memory based on the prediction of the number of remaining register entries in the display FIFO by the programmable emulator.
Abstract:
The present invention provides a personal propulsion device including a body unit having a center of gravity, where the body unit includes a thrust assembly providing a main conduit in fluid communication with at least two thrust nozzles, with the thrust nozzles being located above the center of gravity of the body unit. The thrust nozzles are independently pivotable about a transverse axis located above the center of gravity, and may be independently controlled by a single common linkage. The present invention may further include a base unit having an engine and a pump, which provides pressurized fluid to the body unit through a delivery conduit in fluid communication with both the base unit and the thrust assembly.
Abstract:
A new kind of of multifunctional self-diagnostic device for in-home health-checkup is disclosed. Normal ranges for various test results are stored in the devices″s memory and users can easily tell whether their bio-chemical test response(s) fall within the normal range, and thus providing benefits of early in-home detection subclinical status, inexpensive ways of health checkup, convinient monitoring of diseaase progression, guidance to the application of needed medical treatment, and thus reaching the goal of enhancing the health welfare of the general population.