公开(公告)号：US11621635B2

公开(公告)日：2023-04-04

申请号：US17371785

申请日：2021-07-09

Applicant: Renesas Electronics America Inc.

Inventor： Long Yu ,  Jin Yang ,  Jianhua Yang ,  Pengcheng Tang ,  Xiaodong Zhan

IPC: H02M3/157 ,  H02M3/158 ,  H03K19/20 ,  H03K3/017 ,  H02M1/00

Abstract: Methods and apparatuses for regulating a power converter are described. A device comprising a control circuit and a logic circuit can be integrated in a controller coupled to the power converter. The control circuit can generate a constant off-time signal based on a ramp signal and an error signal. The logic circuit can generate a control signal based on the constant off-time signal and a constant on-time signal. The logic circuit can output the control signal to the power converter. In response to an on-time period of the constant off-time signal being less than an on-time period of the constant on-time signal, the control signal can vary according to the constant on-time signal. In response to the on-time period of the constant off-time signal being greater than the on-time period of the constant on-time signal, the control signal can vary according to the constant off-time signal.

公开(公告)号：US10594218B1

公开(公告)日：2020-03-17

申请号：US16226482

申请日：2018-12-19

Applicant: RENESAS ELECTRONICS AMERICA INC.

Inventor： Xiaodong Zhan ,  Prabhjot Singh ,  Long Yu

IPC: H02M3/158 ,  G05F1/62 ,  H02M3/157

Abstract: A buck boost converter includes a buck boost converter circuit to generate an output voltage in response to an input voltage, and a mode control logic circuit to generate a mode control signal to control an operation mode of the buck boost converter circuit to operate in one of a buck mode, a boost mode, and a buck-boost mode. The buck boost converter circuit includes an upper buck transistor coupled to an input voltage node, the input voltage node to receive the input voltage, an upper boost transistor coupled to an output voltage node, the output voltage node to output the output voltage, and an inductor coupled between the upper buck transistor and the upper boost transistor. The mode control signal is generated based on a first duty cycle of the upper buck transistor and a second duty cycle of the upper boost transistor.