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公开(公告)号：US11245332B1
公开(公告)日：2022-02-08
申请号：US16785155
申请日：2020-02-07
Applicant: Renesas Electronics America Inc.
Inventor： Michael Jason Houston , Allan Warrington
Abstract: One or more embodiments relate to a reference voltage control circuit for a buck-boost converter. According to certain aspects, embodiments can increase or decrease the reference voltage for an error amplifier for controlling a pulse width modulation (PWM) signal when there is a change in the mode of operation. In these and other embodiments, the reference voltage control circuit is configured to modify the reference voltage by increasing or decreasing the reference voltage when there is a change in the mode of operation, so as to reduce overshoot or undershoot disturbances in the regulated output voltage during such transitions.
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公开(公告)号：US11942940B2
公开(公告)日：2024-03-26
申请号：US17345317
申请日：2021-06-11
Applicant: Renesas Electronics America Inc.
Inventor： Aaron Shreeve , Chun Cheung , Michael Jason Houston , Mehul Shah
IPC: H03K3/012 , H03K17/687
CPC classification number: H03K3/012 , H03K17/6871 , H03K2217/0063 , H03K2217/0072
Abstract: Systems, apparatuses, and methods for charging a bootstrap capacitor of a device during low power states are described. In an example, an apparatus can include a controller configured to enable a low power state of the device. The device can include a high side switching element and a low side switching element. The controller can, in response to the low power state of the device being enabled, operate the low side switching element of the device to charge the bootstrap capacitor of the device. The controller can, in response to the low power state of the device being enabled and a level of a control signal being a first level, activate the low side switching element to charge the bootstrap capacitor of the device.
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公开(公告)号：US20220255537A1
公开(公告)日：2022-08-11
申请号：US17345317
申请日：2021-06-11
Applicant: Renesas Electronics America Inc.
Inventor： Aaron Shreeve , Chun Cheung , Michael Jason Houston , Mehul Shah
IPC: H03K3/012 , H03K17/687
Abstract: Systems, apparatuses, and methods for charging a bootstrap capacitor of a device during low power states are described. In an example, an apparatus can include a controller configured to enable a low power state of the device. The device can include a high side switching element and a low side switching element. The controller can, in response to the low power state of the device being enabled, operate the low side switching element of the device to charge the bootstrap capacitor of the device. The controller can, in response to the low power state of the device being enabled and a level of a control signal being a first level, activate the low side switching element to charge the bootstrap capacitor of the device.
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Patent Agency Ranking
公开(公告)号：US12047002B2
公开(公告)日：2024-07-23
申请号：US17567018
申请日：2021-12-31
Applicant: Renesas Electronics America Inc.
Inventor： Michael Jason Houston , Mehul Shah , Warren Schroeder , Akshat Shenoy
CPC classification number: H02M3/1584 , G05F1/575 , H02M1/0009
Abstract: Methods and systems for operating a multiphase voltage regulator are described. The multiphase voltage regulator can include a plurality of power stages. A controller can be connected to the plurality of power stages. The controller can detect a number of activated power stages among the plurality of power stages. The controller can adjust a gain of a current sense feedback loop of the controller to control a load-transient response of the multiphase voltage regulator. The adjustment to the gain can be based on the number of activated power stages.
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公开(公告)号：US20210135679A1
公开(公告)日：2021-05-06
申请号：US17084070
申请日：2020-10-29
Applicant: Renesas Electronics America Inc.
Inventor： Vipul Raithatha , Rob Cox , Allan Warrington , Vinod Aravindakshan Lalithambika , Michael Jason Houston
Abstract: DAC control logic for controlling a DAC for supplying a target voltage VTARGET to a switching converter is disclosed. The DAC logic comprises control logic which is configured, in response to DAC ramp-down, to decrement DAC input code supplied to the DAC in a series of steps. The DAC control logic is configured, for at least some of the steps during ramp down, to wait until at least one switching cycle has occurred in the switching converter before decrementing the DAC input code from a current value to a new value.
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公开(公告)号：US11817785B2
公开(公告)日：2023-11-14
申请号：US17084070
申请日：2020-10-29
Applicant: Renesas Electronics America Inc.
Inventor： Vipul Raithatha , Rob Cox , Allan Warrington , Vinod Aravindakshan Lalithambika , Michael Jason Houston
CPC classification number: H02M3/1582 , H02M3/157 , H02M1/0025
Abstract: DAC control logic for controlling a DAC for supplying a target voltage VTARGET to a switching converter is disclosed. The DAC logic comprises control logic which is configured, in response to DAC ramp-down, to decrement DAC input code supplied to the DAC in a series of steps. The DAC control logic is configured, for at least some of the steps during ramp down, to wait until at least one switching cycle has occurred in the switching converter before decrementing the DAC input code from a current value to a new value.
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公开(公告)号：US11418118B1
公开(公告)日：2022-08-16
申请号：US16785209
申请日：2020-02-07
Applicant: Renesas Electronics America Inc.
Inventor： Michael Jason Houston , Allan Warrington
Abstract: One or more embodiments relate to a regulation loop control circuit for regulation of a parameter such as an input voltage or output voltage for a buck-boost converter. In these and other embodiments, the regulation loop control circuit is configured to select between an input voltage loop for regulation of the input voltage or an output voltage loop for regulation of the output voltage in response to an input voltage error, an output voltage error, and a threshold detector to protect the converter without sacrificing output voltage regulation and transient response.
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公开(公告)号：US11362590B1
公开(公告)日：2022-06-14
申请号：US16785198
申请日：2020-02-07
Applicant: Renesas Electronics America Inc.
Inventor： Michael Jason Houston , Allan Warrington
Abstract: One or more embodiments relate to a current limit mode control circuit for a buck-boost converter which can provide a stable switching of the converter by operating the converter in a current limit mode during an overcurrent condition, performing fewer state transitions while in the current limit mode, and/or by clamping (reducing to a lower value) the output of an error amplifier in the current limit mode for controlling a pulse width modulation (PWM) signal that drives the switching transistors.
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