公开(公告)号：US06373515B1

公开(公告)日：2002-04-16

申请号：US09635177

申请日：2000-08-09

Applicant: Robert D. Morrison

Inventor： Robert D. Morrison

IPC: B41J2435

CPC classification number: H04N1/053 ,  G06K15/1223 ,  H04N1/1135 ,  H04N1/12 ,  H04N2201/02443 ,  H04N2201/04767 ,  H04N2201/04798

Abstract: A variable resolution transition placement circuit in an electrophotographic imaging device allows transitions to be placed within a stream of video data so that the pixel resolution achieved over a scan line is adjustable on a pixel by pixel basis using a system clock. Pixel data defines transition positions relative to a synthesized video clock defining pixel time periods. A converter converts positions of the transitions relative to the synthesized video clock to positions relative to the system clock using a value provided by a synthesized video clock to system clock transform generator. The value can change between synthesized video clock cycles to change the pixel resolution. A synthesized video generator generates values of a synthesized video clock relative to the system clock. Offset values generated from values of the synthesized video clock, the positions of the transitions relative to the system clock, and phase difference values from a phase measuring device are combined to determine the positions at which the transitions will be generated relative to the system clock. The values representing the positions at which the transitions will be generated are stored in a transition queue. The integer portions of these values are decremented on each system clock cycle. When the integer portions of these values reach zero, the fractional portion of these values (representing the position of transitions within system clock clock cycles) are provided to transition generation logic to generate transitions at the specified positions in system clock cycles.

Abstract translation: 电子照相成像装置中的可变分辨率转移放置电路允许将转变放置在视频数据流内，使得使用系统时钟逐像素地在扫描线上实现的像素分辨率是可调节的。 像素数据定义了相对于定义像素时间段的合成视频时钟的转换位置。 A转换器使用由合成视频时钟提供给系统时钟变换发生器的值将相对于合成视频时钟的转变的位置转换为相对于系统时钟的位置。 该值可以在合成的视频时钟周期之间改变以改变像素分辨率。 合成视频发生器产生相对于系统时钟的合成视频时钟的值。 从合成视频时钟的值，相对于系统时钟的转变位置和相位测量装置的相位差产生的偏移值被组合以确定相对于系统时钟将产生转换的位置。 表示将生成转换的位置的值存储在转换队列中。 这些值的整数部分在每个系统时钟周期内递减。 当这些值的整数部分达到零时，这些值的小数部分（表示系统时钟周期内的转换位置）被提供给转换生成逻辑，以在系统时钟周期中的指定位置产生转换。

公开(公告)号：US06340986B1

公开(公告)日：2002-01-22

申请号：US09534747

申请日：2000-03-24

Applicant: Robert D. Morrison ,  Eugene A. Roylance

Inventor： Robert D. Morrison ,  Eugene A. Roylance

IPC: B41J2435

CPC classification number: H04N1/053 ,  G06K15/1223 ,  H04N1/1135 ,  H04N1/12 ,  H04N2201/04784

Abstract: An electrophotographic imaging device uses a transition placement device to position transitions in a stream of video data. A rasterizer included in the electrophotographic imaging device generates pixel data bytes based upon data received from a computer defining an image. A converter generates codes specifying positions of transitions within a pixel time period corresponding to a pixel data byte. The transition placement device includes a phase measuring device to measure a timing offset between an active edge of a beam detect signal and a rising edge of a reference clock. A transition adjustment device adjusts the positions of the transitions specified by the codes relative to the rising edge of the reference clock using the timing offset. Transition generation logic generates the transitions for the stream of video data using the adjusted transition positions received from the transition adjustment device. If the adjusted positions of the transitions shift the occurrence of the transitions to the next cycle of the reference clock, the transition adjustment device determines the position of the transitions relative to the rising edge of the reference clock into which the transitions were shifted. Registers included in a next cycle transition storage device delay the transitions shifted to the next cycle by one reference clock cycle before application to the transition generation logic.

Abstract translation: 电子照相成像设备使用过渡放置设备来定位视频数据流中的过渡。 包括在电子照相成像设备中的光栅化器基于从定义图像的计算机接收的数据生成像素数据字节。 A转换器产生指定对应于像素数据字节的像素时间段内的转换位置的代码。 过渡放置装置包括相位测量装置，用于测量光束检测信号的有效边沿和参考时钟的上升沿之间的定时偏移。 转换调整装置使用定时偏移来调整代码相对于参考时钟的上升沿指定的转变的位置。 转换生成逻辑使用从转换调整装置接收到的经调整的转换位置来生成视频数据流的转换。 如果转换的调整位置将转换的发生移动到参考时钟的下一个周期，则转换调整装置确定转变相对于转换偏移到的基准时钟的上升沿的位置。 包括在下一个周期转换存储设备中的寄存器在应用到转换生成逻辑之前将转移到下一个周期的转移延迟一个参考时钟周期。

公开(公告)号：US5760816A

公开(公告)日：1998-06-02

申请号：US596032

申请日：1996-02-06

Applicant: Robert D. Morrison

Inventor： Robert D. Morrison

IPC: B41J2/44 ,  G06F1/06 ,  G06K15/12 ,  H03K5/15 ,  H04N1/053 ,  H04N1/113 ,  H04N1/12 ,  B41J2/47

CPC classification number: H04N1/053 ,  G06K15/1219 ,  H04N1/1135 ,  H04N1/12 ,  H04N2201/0471 ,  H04N2201/04784

Abstract: An electrophotographic printer includes a photoreceptor on a drum or belt, a laser beam that is reciprocally scanned thereacross, a beam detect signal circuit for generating a beam detect signal and an asynchronous clock oscillator for generating clock pulses. The printer also includes circuitry for generating a plurality of clock signals that are phase synchronized with the beam detect signal. The circuitry includes a tapped delay line for receiving the asynchronous clock pulses, each tap outputting a delayed clock pulse train. A register/selector circuit is coupled to the taps and is responsive to a transition of the beam detect signal for determining a tap which outputs a 0.degree. phase clock transition that is closely proximate to the beam detect signal. Phase delay logic provides signals indicative of which taps of the delay line circuit manifest clock pulse trains that are closest in time to leading and lagging edges of a 0.degree. phase clock pulse, respectively. The phase delay logic circuit further determines taps of the delay line circuit that are intermediate the aforesaid taps and which of those taps should be utilized to provide delayed clock signals of a fractional phase. Signals from the selected taps are thereafter switched to output circuits.

Abstract translation: 电子照相打印机包括在感光鼓或皮带上的感光体，在其上往复扫描的激光束，用于产生光束检测信号的光束检测信号电路和用于产生时钟脉冲的异步时钟振荡器。 打印机还包括用于产生与光束检测信号相位同步的多个时钟信号的电路。 电路包括用于接收异步时钟脉冲的抽头延迟线，每个抽头输出延迟时钟脉冲串。 寄存器/选择器电路耦合到抽头，并且响应于光束检测信号的转变，用于确定输出接近光束检测信号的0度相位时钟转变的抽头。 相位延迟逻辑提供指示延迟线电路的哪些抽头分别表示时间上与0度相位时钟脉冲的前沿和滞后沿最接近的时钟脉冲串的信号。 相位延迟逻辑电路进一步确定延迟线电路的抽头，这些抽头位于上述抽头之间，并且这些抽头中的哪一个应用于提供分数阶段的延迟时钟信号。 然后将来自所选抽头的信号切换到输出电路。

公开(公告)号：US06366307B1

公开(公告)日：2002-04-02

申请号：US09534803

申请日：2000-03-24

Applicant: Robert D. Morrison

Inventor： Robert D. Morrison

IPC: B41J2435

CPC classification number: H04N1/0446 ,  G06K15/1223 ,  H04N1/053 ,  H04N1/1135 ,  H04N1/12 ,  H04N1/4056 ,  H04N2201/02443 ,  H04N2201/0471 ,  H04N2201/04732 ,  H04N2201/04744 ,  H04N2201/04781 ,  H04N2201/04798

Abstract: A system is provided for enabling a pulse width modulator to render video data for a laser at a frequency independent of the operating frequency of the pulse width modulator. The system includes phase measuring circuitry, edge output determining circuitry, edge location circuitry, and a summer. The phase measuring circuitry is operative to detect a phase offset on a scan line for a laser. The edge output determining circuitry is operative to determine which system clock cycle to output an edge on the system clock to act as if it were on a video clock. The edge location circuitry is operative to locate placement of an edge for a given pixel. The summer communicates with the phase measuring circuitry, the edge output determining circuitry, and the edge location circuitry. The summer is operative to combine values from the phase measuring circuitry, the edge output determining circuitry, and the edge location circuitry to generate a desired video signal. A method is also provided.

Abstract translation: 提供了一种用于使得脉冲宽度调制器能够以与脉冲宽度调制器的工作频率无关的频率来呈现激光器的视频数据的系统。 该系统包括相位测量电路，边缘输出确定电路，边缘位置电路和夏季。 相位测量电路用于检测用于激光的扫描线上的相位偏移。 边缘输出确定电路可操作以确定哪个系统时钟周期输出系统时钟上的边沿以如同在视频时钟上一样工作。 边缘位置电路用于定位给定像素的边缘的位置。 夏天与相位测量电路，边沿输出确定电路和边缘位置电路进行通信。 该夏季用于组合来自相位测量电路，边缘输出确定电路和边缘位置电路的值以产生期望的视频信号。 还提供了一种方法。

公开(公告)号：US06236427B1

公开(公告)日：2001-05-22

申请号：US09491995

申请日：2000-01-26

Applicant: Eugene A. Roylance ,  Robert D. Morrison

Inventor： Eugene A. Roylance ,  Robert D. Morrison

IPC: B41J2435

CPC classification number: G06K15/1223 ,  H04N1/053 ,  H04N1/1135 ,  H04N1/12 ,  H04N2201/04784

Abstract: An embodiment of an edge placement device is supplied with transition data to generate transitions during a pixel time period corresponding to the transition data. The transition data is supplied by pulse code logic that converts pixel data to the transition data. The embodiment of an edge placement device includes first edge placement logic coupled to taps from a first clock delay chain and second edge placement logic coupled to taps of a second clock phase delay chain. Also included is a phase splitter that generate a first and a second clock phase coupled, respectively, to the first and the second clock delay chain from a clock corresponding to a pixel time period. The first and the second clock phase have rising edges on alternate cycles of the clock. The first and the second edge placement logic each include a plurality of D flip flops. The clock inputs of each of the flip flops in the first and the second edge placement logic are coupled, respectively, to one tap from first or the second clock delay chain. The D inputs of the flip flops of the first and the second placement edge placement logic are coupled, respectively, to a first and a second data phase provided by the pulse code logic. By setting the values of the first and the second data phases, supplied on alternate cycles of the clock, video data is generated having transitions during the pixel time period corresponding to the pixel data.

Abstract translation: 向边缘放置装置的实施例提供过渡数据，以在对应于转换数据的像素时间段期间产生转变。 转换数据由将像素数据转换为转换数据的脉冲代码逻辑提供。 边缘放置装置的实施例包括耦合到来自第一时钟延迟链的抽头和耦合到第二时钟相位延迟链的抽头的第二边缘放置逻辑的第一边缘放置逻辑。 还包括一个分相器，其产生从对应于像素时间周期的时钟分别耦合到第一和第二时钟延迟链的第一和第二时钟相位。 第一和第二时钟相位在时钟的交替周期上具有上升沿。 第一和第二边缘放置逻辑每个包括多个D触发器。 第一和第二边缘放置逻辑中的每个触发器的时钟输入分别被耦合到来自第一或第二时钟延迟链的一个抽头。 第一和第二放置边缘放置逻辑的触发器的D输入分别耦合到由脉冲代码逻辑提供的第一和第二数据相位。 通过设置在时钟的交替周期提供的第一和第二数据相位的值，生成在对应于像素数据的像素时间周期期间具有转变的视频数据。

公开(公告)号：US5990923A

公开(公告)日：1999-11-23

申请号：US970816

申请日：1997-11-14

Applicant: Robert D. Morrison

Inventor： Robert D. Morrison

IPC: G02B26/10 ,  G06K15/12 ,  H04N1/405 ,  B41J2/47

CPC classification number: G06K15/1219 ,  H04N1/4056

Abstract: Pulse width modulation of signals, such as provided to a driver in a laser printer, is phase locked to a beam detect signal. In addition, it must permit continuously variable, arbitrarily small pulses at extremely high speeds. This invention describes a novel method and system using multiple streams of variable phase clocked outputs. The variable phase clocked outputs are combined with a clock generator to achieve these goals at low cost. As a result, the pulse width modulated signals provide continuously variable selectable pulse widths at extremely high speed.

Abstract translation: 诸如提供给激光打印机中的驱动器的信号的脉冲宽度调制被锁相到光束检测信号。 此外，它必须允许以非常高的速度连续变化，任意小的脉冲。 本发明描述了一种使用多个可变相位时钟输出流的新颖方法和系统。 可变相位时钟输出与时钟发生器组合以低成本实现这些目标。 结果，脉冲宽度调制信号以极高的速度提供连续可变的可选脉冲宽度。

公开(公告)号：US5438353A

公开(公告)日：1995-08-01

申请号：US969913

申请日：1992-11-02

Applicant: Robert D. Morrison

Inventor： Robert D. Morrison

IPC: G06K15/12 ,  H04N1/053 ,  H04N1/12 ,  G01D9/42

CPC classification number: H04N1/053 ,  G06K15/1219 ,  H04N1/12 ,  H04N2201/0471 ,  H04N2201/04784

Abstract: A new and improved method and system for controlling the timing of a modulation input signal utilized for driving a laser engine of a laser or electrophotographic printer. This method and system utilizes a novel modulation generator circuit which operates to receive both a beam detect signal from the laser driver circuit and an asynchronous clock signal from the output of an asynchronous clock generator. The modulation generator in turn operates to delay the output signal from the asynchronous clock generator a predetermined number of times and then select the delayed clock signal which is closest in phase to the phase of the beam detect signal. Then this clock generated signal is used to set the modulation frequency of a bi-phase output digital clock signal from the modulation generator which is applied as input timing signal for video input data applied to laser driver circuit and used for developing images on a photoconductive drum.

Abstract translation: 一种用于控制用于驱动激光或电子照相打印机的激光引擎的调制输入信号的定时的新的和改进的方法和系统。 该方法和系统利用了一种新颖的调制发生器电路，其操作以接收来自激光驱动电路的波束检测信号和来自异步时钟发生器的输出的异步时钟信号。 调制发生器又工作以将来自异步时钟发生器的输出信号延迟预定次数，然后选择与波束检测信号的相位最相同的延迟时钟信号。 然后，该时钟产生信号用于设置来自调制发生器的双相输出数字时钟信号的调制频率，该调制发生器作为施加到激光驱动电路并用于在感光鼓上显影图像的视频输入数据的输入定时信号 。

公开(公告)号：US07061519B2

公开(公告)日：2006-06-13

申请号：US10638623

申请日：2003-08-09

Applicant: Robert D. Morrison

Inventor： Robert D. Morrison

IPC: B41U2/47

CPC classification number: H04N1/393 ,  G06T3/40

Abstract: A method for scaling an image includes determining a plurality of lineweight values for a plurality of virtual scan lines. In addition, the method includes determining a normalization value using the plurality of lineweight values. The method further includes determining a pulse code value for a pixel in an actual scan line using the plurality of lineweight values, the normalization value, and pulse code values for pixels in the plurality of virtual scan lines.

Abstract translation: 用于缩放图像的方法包括确定多个虚拟扫描线的多个线宽值。 另外，该方法包括使用多个线值来确定归一化值。 该方法还包括使用多个虚拟扫描线中的像素的多个线宽值，归一化值和脉冲编码值来确定实际扫描线中的像素的脉冲编码值。

公开(公告)号：US06842055B1

公开(公告)日：2005-01-11

申请号：US10639818

申请日：2003-08-13

Applicant: Robert D. Morrison

Inventor： Robert D. Morrison

IPC: G06F1/10 ,  G06F1/04 ,  G06F1/08 ,  G06F1/12 ,  H03K3/00 ,  H03K5/05 ,  H03K5/13 ,  H03K19/173 ,  H03L7/00 ,  H03L7/07 ,  H03L7/081

CPC classification number: H03L7/07 ,  H03L7/0814

Abstract: Circuits and methods are provided for clock adjustment. A method for clock adjustment includes receiving feedback clocks from independent ASIC modules. The method includes comparing the feedback clocks to a reference clock to generate phase measurement values. A common delay is removed from the phase measurement values to form normalized correction values. Target phase values and clock select values are selected using the normalized correction values. And, clock signals to independent ASIC modules are adjusted based on the target phase values and clock select values.

公开(公告)号：US06437553B1

公开(公告)日：2002-08-20

申请号：US09675918

申请日：2000-09-29

Applicant: Mark W. Maloney ,  Eugene A. Roylance ,  Robert D. Morrison

Inventor： Mark W. Maloney ,  Eugene A. Roylance ,  Robert D. Morrison

IPC: G01R2500

CPC classification number: G01R31/3016 ,  H03K3/0315 ,  H03K5/133

Abstract: The present invention provides both differential and integral non-linearity measurement capabilities with a minimum of additional hardware and a test time reduction of several orders of magnitude. The test circuit for N delay lines includes a ring oscillator that has a select signal and an output. A counter is connected in parallel with the ring oscillator. An arithmetic logic unit receives a “COMPARE” value from a register and the counter output. An upper and a lower bound register store acceptable tolerances for non-linearity. Each comparator, upper and lower bound, receives the tolerance stored in the corresponding register and the output of the arithmetic logic unit. An AND gate receives the outputs of the upper and lower bound comparators and generates a signal indicative of the state of the oscillator.

Abstract translation: 本发明提供差分和积分非线性测量能力，具有最小的附加硬件和几个数量级的测试时间减少。 用于N个延迟线的测试电路包括具有选择信号和输出的环形振荡器。 计数器与环形振荡器并联连接。 算术逻辑单元从寄存器和计数器输出接收“COMPARE”值。 上限和下限寄存器存储非线性的可接受公差。 每个比较器上限和下限接收存储在相应寄存器中的公差和算术逻辑单元的输出。 与门接收上限和下限比较器的输出，并产生指示振荡器状态的信号。