公开(公告)号：US12288586B2

公开(公告)日：2025-04-29

申请号：US17952857

申请日：2022-09-26

Applicant: SanDisk Technologies LLC

Inventor： Ramy Nashed Bassely Said ,  Jiahui Yuan ,  Lito De La Rama

IPC: G11C16/04 ,  G06F3/06 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  H01L25/065

Abstract: To reduce data disturbs and lower current requirements of a 3D NAND memory die, a multi-block plane of non-volatile memory cells has its source line separated into multiple source line regions by introduction of isolation trenches. The plane structure for the NAND memory is maintained, but is broken into multi-block sub-planes, each with an independently biasable source line.

公开(公告)号：US12249378B2

公开(公告)日：2025-03-11

申请号：US17666810

申请日：2022-02-08

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Deepanshu Dutta ,  Sarath Puthenthermadam ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

Abstract: A non-volatile semiconductor memory device, described herein, comprises a bit line, a source line, a memory string comprising a plurality of memory cells connected in series between the source line and the bit line, and control circuitry coupled to the plurality of memory cells, the source line, and the bit line. The control circuitry is configured to: determine if a program operation is a single-bit program operation or multi-bit program operation; in response to the determination, identify a voltage level to set the source line to during performance of the program operation; and perform the program operation on the memory string, the program operation including setting the source line to the voltage level.

公开(公告)号：US12176032B2

公开(公告)日：2024-12-24

申请号：US17898006

申请日：2022-08-29

Applicant: SanDisk Technologies LLC

Inventor： Abu Naser Zainuddin ,  Jiahui Yuan ,  Towhidur Razzak

IPC: G11C16/08 ,  G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C29/12 ,  H01L25/065 ,  H01L23/00

Abstract: Different ramp rates for different regions, or zones, of word lines are used for the pass voltage applied to unselected word lines during a program operation. The properties of the word lines, such as their resistance and capacitance (RC) values, vary across the NAND memory array. By determining the RC values of the word lines across the array, the word lines can be broken into multiple zones based on these properties. The zones can then be individually assigned different ramp rates for applying a pass voltage to the unselected word lines, where a parameter for the ramp rates can be stored as a register value on the memory die.

公开(公告)号：US20240233841A9

公开(公告)日：2024-07-11

申请号：US18357489

申请日：2023-07-24

Applicant: SanDisk Technologies LLC

Inventor： Abu Naser Zainuddin ,  Jiahui Yuan ,  Toru Miwa

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  H01L25/0657

Abstract: A memory system programs memory cells connected to a selected word line by applying doses of programming and performing program-verify between doses. An efficient and low current program-verify operation includes: while scanning the results of a previous program-verify operation, ramp up voltages on the select lines for the next program-verify operation without waiting for the scan to complete and ramp up voltages on unselected word lines for the next program-verify operation following a step signal (so that voltage applied to the unselected word lines rise in steps) without waiting for the scan to complete.

公开(公告)号：US20240203512A1

公开(公告)日：2024-06-20

申请号：US18355343

申请日：2023-07-19

Applicant: SanDisk Technologies LLC

Inventor： Longju Liu ,  Sarath Puthenthermadam ,  Jiahui Yuan

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/10

Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells in a plurality of program loops, determine that the first set of the non-volatile memory cells passes verification to a particular programmed state in a first number of program loops, determine a first voltage based on the first number of program loops, add an adaptive voltage offset to the first voltage to obtain a second voltage, and program a second set of the non-volatile memory cells in a plurality of program loops using the second voltage. The adaptive voltage offset varies as a function of temperature.

公开(公告)号：US20240194277A1

公开(公告)日：2024-06-13

申请号：US18360306

申请日：2023-07-27

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiang Yang ,  Yi Song ,  Jiahui Yuan

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/26

Abstract: Technology is disclosed herein for a memory system that includes control circuits that are configured to connect to a three-dimensional memory structure. The memory structure includes NAND strings arranged in a plurality of rows, a plurality of bit lines connected to the NAND strings and a plurality of word lines, each word line coupled to the plurality of rows of NAND strings. The control circuits are configured to, in a program-verify operation, sense memory cells of a first row of NAND strings coupled to the selected word line for a first sense time and sense memory cells of a second row of NAND strings coupled to the selected word line for a second sense time while applying a program-verify voltage to the selected word line.

公开(公告)号：US11972814B2

公开(公告)日：2024-04-30

申请号：US17701320

申请日：2022-03-22

Applicant: SanDisk Technologies LLC

Inventor： Xue Bai Pitner ,  Yu-Chung Lien ,  Ravi Kumar ,  Jiahui Yuan ,  Bo Lei ,  Zhenni Wan

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3404

Abstract: The memory device includes a plurality of memory cells, which include a first set of memory cells and a second set of memory cells. A controller is in communication with the memory cells. The controller is configured to, in a first programming pass and then a second programming pass, program the memory cells of the first and second sets to respective final threshold voltages associated with a plurality of programmed data states. The controller is further configured to, in the first programming pass, verify the first set of memory cells at a first set of checkpoint data states and verify the second set of memory cells at a second set of checkpoint data states that is different than the first set of checkpoint data states.

公开(公告)号：US20240105262A1

公开(公告)日：2024-03-28

申请号：US17952857

申请日：2022-09-26

Applicant: SanDisk Technologies LLC

Inventor： Ramy Nashed Bassely Said ,  Jiahui Yuan ,  Lito De La Rama

IPC: G11C16/04 ,  G06F3/06 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G06F3/0619 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  H01L25/0657

Abstract: To reduce data disturbs and lower current requirements of a 3D NAND memory die, a multi-block plane of non-volatile memory cells has its source line separated into multiple source line regions by introduction of isolation trenches. The plane structure for the NAND memory is maintained, but is broken into multi-block sub-planes, each with an independently biasable source line.

公开(公告)号：US20240086074A1

公开(公告)日：2024-03-14

申请号：US17940465

申请日：2022-09-08

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Jiahui Yuan ,  Yanjie Wang

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679

Abstract: An apparatus includes a control circuit configured to connect to NAND strings that are connected to bit lines, where each bit line is connected to a plurality of NAND strings in a corresponding plurality of regions of a block. The control circuit is configured to apply a read voltage in read operations directed to NAND strings of the plurality of regions of the block and subsequently adjust the read voltage by a first predetermined amount for read operations directed to NAND strings of a first region of the block. The control circuit is further configured to adjust the read voltage by a second predetermined amount for read operations directed to NAND strings of a second region of the block. The first and second predetermined amounts are based on respective locations of the first and second regions in the block.

公开(公告)号：US20240036740A1

公开(公告)日：2024-02-01

申请号：US17983870

申请日：2022-11-09

Applicant: SanDisk Technologies LLC

Inventor： Yihang Liu ,  Xiaochen Zhu ,  Jie Liu ,  Sarath Puthenthermadam ,  Jiahui Yuan ,  Feng Gao

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/064 ,  G06F3/0679

Abstract: A non-volatile memory system separately performs a memory operation for multiple sub-blocks of a block in order from previously determined slowest sub-block of the block to a previously determined faster sub-block of the block. As a slower sub-block is more likely to fail, this order of is more likely to identify a failure earlier in the process thereby saving time and reducing potential for a disturb. In some embodiments, the proposed order of operation can be used in conjunction with a programming process that concurrently programs blocks in multiple planes using completion of programming of a fastest plane to a data state as a trigger to test for program failure of other planes to the data state.