公开(公告)号：US12185540B2

公开(公告)日：2024-12-31

申请号：US17523447

申请日：2021-11-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michiaki Sano ,  Yusuke Mukae ,  Naoki Takeguchi ,  Yujin Terasawa ,  Tatsuya Hinoue ,  Ramy Nashed Bassely Said

IPC: H10B43/27 ,  H10B41/27

Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.

公开(公告)号：US12160989B2

公开(公告)日：2024-12-03

申请号：US17716698

申请日：2022-04-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely Said ,  Raghuveer S. Makala ,  Jiahui Yuan ,  Senaka Kanakamedala

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and a drain-select-level isolation structure. One of the insulating layers is a composite insulating layer including an insulating-material-containing sublayer consisting essentially of an insulating material and an etch stop dielectric material sublayer having a material composition that is different from the insulating material. The etch stop dielectric material sublayer can be employed as an etch stop structure during formation of the drain-select-level isolation structure through drain-select-level electrically conductive layers.

公开(公告)号：US11749736B2

公开(公告)日：2023-09-05

申请号：US17189153

申请日：2021-03-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xue Bai Pitner ,  Raghuveer S. Makala ,  Fei Zhou ,  Senaka Kanakamedala ,  Ramy Nashed Bassely Said

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/78 ,  H10B41/27 ,  H10B43/27 ,  H10B51/20

CPC classification number: H01L29/42364 ,  H01L29/40111 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/7827 ,  H10B41/27 ,  H10B43/27 ,  H10B51/20

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and memory opening fill structures located in the memory opening and including a vertical semiconductor channel, a dielectric material liner laterally surrounding the vertical semiconductor channel, and a vertical stack of discrete memory elements laterally surrounding the dielectric material liner. A subset of the insulating layers a lower insulating sublayer, an upper insulating sublayer overlying the lower insulating sublayer, and a center insulating sublayer located between and in contact with the lower insulating sublayer and the upper insulating sublayer.

公开(公告)号：US11387250B2

公开(公告)日：2022-07-12

申请号：US16722745

申请日：2019-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely Said ,  Senaka Kanakamedala ,  Fei Zhou ,  Raghuveer S. Makala ,  Yao-Sheng Lee

IPC: H01L27/11582 ,  H01L21/02

Abstract: A three-dimensional memory device includes a vertically alternating stack of insulating layers and electrically conductive layers located over a top surface of a substrate and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a respective memory film and a respective vertical semiconductor channel, and each of the insulating layers contains a metal-organic framework (MOF) material portion. The MOF material portion has a low dielectric constant, and reduces RC coupling between the electrically conductive layers. An optional airgap may be located within the MOF material portion to further reduce the effective dielectric constant. Optionally, discrete charge storage regions or floating gates may be formed only at the levels of the electrically conductive layers to reduce program disturb and noise in the device.

公开(公告)号：US12288586B2

公开(公告)日：2025-04-29

申请号：US17952857

申请日：2022-09-26

Applicant: SanDisk Technologies LLC

Inventor： Ramy Nashed Bassely Said ,  Jiahui Yuan ,  Lito De La Rama

IPC: G11C16/04 ,  G06F3/06 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  H01L25/065

Abstract: To reduce data disturbs and lower current requirements of a 3D NAND memory die, a multi-block plane of non-volatile memory cells has its source line separated into multiple source line regions by introduction of isolation trenches. The plane structure for the NAND memory is maintained, but is broken into multi-block sub-planes, each with an independently biasable source line.

公开(公告)号：US12267998B2

公开(公告)日：2025-04-01

申请号：US17543987

申请日：2021-12-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Kartik Sondhi ,  Ramy Nashed Bassely Said ,  Senaka Kanakamedala

IPC: H10B43/27 ,  H10B41/27 ,  H10D30/68 ,  H10D30/69 ,  H10D64/01

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel and a memory film. The memory film includes a contoured blocking dielectric layer including sac-shaped lateral protrusions located at levels of the electrically conductive layers, a tunneling dielectric layer in contact with the vertical semiconductor channel, and a vertical stack of charge storage material portions located within volumes enclosed by the sac-shaped lateral protrusions.

公开(公告)号：US20240105262A1

公开(公告)日：2024-03-28

申请号：US17952857

申请日：2022-09-26

Applicant: SanDisk Technologies LLC

Inventor： Ramy Nashed Bassely Said ,  Jiahui Yuan ,  Lito De La Rama

IPC: G11C16/04 ,  G06F3/06 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G06F3/0619 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  H01L25/0657

Abstract: To reduce data disturbs and lower current requirements of a 3D NAND memory die, a multi-block plane of non-volatile memory cells has its source line separated into multiple source line regions by introduction of isolation trenches. The plane structure for the NAND memory is maintained, but is broken into multi-block sub-planes, each with an independently biasable source line.

公开(公告)号：US11515273B2

公开(公告)日：2022-11-29

申请号：US16851839

申请日：2020-04-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely Said ,  Senaka Kanakamedala ,  Raghuveer S. Makala

IPC: H01L23/00 ,  H01L23/522 ,  H01L25/065

Abstract: At least one polymer material may be employed to facilitate bonding between the semiconductor dies. Plasma treatment, formation of a blended polymer, or formation of polymer hairs may be employed to enhance bonding. Alternatively, air gaps can be formed by subsequently removing the polymer material to reduce capacitive coupling between adjacent bonding pads.

公开(公告)号：US11430736B2

公开(公告)日：2022-08-30

申请号：US17000934

申请日：2020-08-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely Said ,  Raghuveer S. Makala ,  Senaka Kanakamedala ,  Yao-Sheng Lee

IPC: H01L23/535 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L27/11582

Abstract: A semiconductor structure includes first metal lines located above at least one semiconductor device, and a continuous metal organic framework (MOF) material layer including lower MOF portions that are located between neighboring pairs of first metal lines and an upper MOF matrix portion that continuously extends over the first metal lines and connected to each of the lower MOF portions.

公开(公告)号：US12150302B2

公开(公告)日：2024-11-19

申请号：US17679335

申请日：2022-02-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely Said ,  Senaka Kanakamedala ,  Raghuveer S. Makala ,  Peng Zhang ,  Yanli Zhang

IPC: H01L27/11582 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening fill structure including a vertical semiconductor channel and a memory film. The memory film includes a tunneling dielectric layer in contact with the vertical semiconductor channel, a first vertical stack of first dielectric oxide material portions located at levels of the insulating layers and including a dielectric oxide material of a first element, and a second vertical stack of second dielectric oxide material portions located at levels of the electrically conductive layers and including a mixed dielectric oxide material that is a dielectric oxide material of the first element and a second element.