公开(公告)号：US10188001B2

公开(公告)日：2019-01-22

申请号：US14603191

申请日：2015-01-22

Applicant: Sanmina Corporation

Inventor： Douglas Ward Thomas ,  Shinichi Iketani ,  Dale Kersten

IPC: H05K3/42 ,  H05K1/02 ,  H05K3/24

Abstract: The present invention relates to printed circuit boards (PCBs), and more particularly, to methods of forming high aspect ratio through holes and high precision stub removal in a printed circuit board (PCB). The high precision stub removal processes may be utilized in removing long stubs and short stubs. In the methods, multiple holes of varying diameter and depth are drilled from an upper and/or lower surface of the printed circuit board utilizing drills of different diameters.

公开(公告)号：US10446356B2

公开(公告)日：2019-10-15

申请号：US15784070

申请日：2017-10-13

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Douglas Ward Thomas

IPC: H01H85/12 ,  H01H85/055 ,  H01H85/20 ,  H01H85/30 ,  H01H85/56 ,  H05K1/11 ,  H05K1/14 ,  H05K3/00 ,  H05K3/10 ,  H05K3/40 ,  H05K3/46 ,  H01H85/00 ,  H01H85/143 ,  H01H1/58 ,  H01H85/02 ,  H05K3/06 ,  H01H85/06

Abstract: A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core. A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A conductive material is then plated to an inner surface of the second hole.

公开(公告)号：US09661758B2

公开(公告)日：2017-05-23

申请号：US14463588

申请日：2014-08-19

Applicant: Sanmina Corporation

Inventor： Douglas Ward Thomas ,  Shinichi Iketani

IPC: H05K3/10 ,  H05K3/42 ,  H05K3/00

CPC classification number: H05K3/427 ,  H05K3/0026 ,  H05K3/0047 ,  H05K2201/09845 ,  H05K2203/0207 ,  Y10T29/49165

Abstract: Cost effective and efficient methods to maximize printed circuit board (PCB) utilization with minimized signal degradation are provided. The methods include electrically isolating a segmented via structure by controlling the formation of a conductive material within a plated via structure by utilizing different diameter drills within a via structure for trimming the conductive material at the via shoulder (i.e., the rim of a drilled two diameter hole boundary). The trimmed portion may be voided in the via structure for allowing electrically isolated plated through-hole (PTH) segments. One or more areas of trimmed rims within the via structure are used to form multiple stair like diameter holes to create one or more voids in the via structure. As a result, the formation of conductive material within the via structure may be limited to those areas necessary for the transmission of electrical signals.

公开(公告)号：US20200043690A1

公开(公告)日：2020-02-06

申请号：US16601068

申请日：2019-10-14

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Douglas Ward Thomas

IPC: H01H85/12 ,  H05K3/46 ,  H05K3/40 ,  H05K3/10 ,  H05K3/00 ,  H05K1/14 ,  H05K1/11 ,  H01H85/56 ,  H01H85/30 ,  H01H85/20 ,  H01H85/055 ,  H01H85/143 ,  H01H85/00

Abstract: A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core. A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A conductive material is then plated to an inner surface of the second hole.

公开(公告)号：US20180110133A1

公开(公告)日：2018-04-19

申请号：US15784070

申请日：2017-10-13

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Douglas Ward Thomas

IPC: H05K3/46 ,  H05K3/00 ,  H05K1/14 ,  H05K3/40 ,  H05K1/11 ,  H05K3/10

CPC classification number: H01H85/12 ,  H01H85/0013 ,  H01H85/055 ,  H01H85/06 ,  H01H85/143 ,  H01H85/20 ,  H01H85/306 ,  H01H85/56 ,  H01H2001/5877 ,  H01H2085/025 ,  H01H2085/0555 ,  H05K1/115 ,  H05K1/144 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/108 ,  H05K3/4076 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4638 ,  H05K2201/0338 ,  H05K2201/041 ,  H05K2201/09227 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/1438 ,  H05K2203/166 ,  Y10T29/49165

Abstract: A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core. A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A conductive material is then plated to an inner surface of the second hole.

公开(公告)号：US10811210B2

公开(公告)日：2020-10-20

申请号：US16601068

申请日：2019-10-14

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Douglas Ward Thomas

IPC: G06K9/62 ,  G11C15/00 ,  G11C17/10 ,  G11C15/04 ,  H01H85/12 ,  H01H85/00 ,  H01H85/143 ,  H05K3/46 ,  H01H85/055 ,  H01H85/20 ,  H01H85/30 ,  H01H85/56 ,  H05K1/11 ,  H05K1/14 ,  H05K3/00 ,  H05K3/10 ,  H05K3/40 ,  H01H85/06 ,  H01H1/58 ,  H01H85/02 ,  H05K3/06

Abstract: A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core. A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A conductive material is then plated to an inner surface of the second hole.

公开(公告)号：US20150047188A1

公开(公告)日：2015-02-19

申请号：US14463588

申请日：2014-08-19

Applicant: Sanmina Corporation

Inventor： Douglas Ward Thomas ,  Shinichi Iketani

IPC: H05K3/42

CPC classification number: H05K3/427 ,  H05K3/0026 ,  H05K3/0047 ,  H05K2201/09845 ,  H05K2203/0207 ,  Y10T29/49165

Abstract: Cost effective and efficient methods to maximize printed circuit board (PCB) utilization with minimized signal degradation are provided. The methods include electrically isolating a segmented via structure by controlling the formation of a conductive material within a plated via structure by utilizing different diameter drills within a via structure for trimming the conductive material at the via shoulder (i.e., the rim of a drilled two diameter hole boundary). The trimmed portion may be voided in the via structure for allowing electrically isolated plated through-hole (PTH) segments. One or more areas of trimmed rims within the via structure are used to form multiple stair like diameter holes to create one or more voids in the via structure. As a result, the formation of conductive material within the via structure may be limited to those areas necessary for the transmission of electrical signals.

Abstract translation: 提供了以最小的信号劣化来最大化印刷电路板（PCB）利用率的成本有效和高效的方法。 所述方法包括通过在通孔结构内利用不同直径的钻头来控制在通孔结构内的导电材料的形成来控制电镀过孔结构内的导电材料的形成来电隔离分段通孔结构，以用于修整通孔肩部处的导电材料（即，钻孔两个直径的边缘 孔边界）。 修整部分可以在通孔结构中被排除，以允许电隔离的电镀通孔（PTH）段。 通孔结构内的一个或多个修剪边缘的区域用于形成多个阶梯状直径孔，以在通孔结构中产生一个或多个空隙。 结果，通孔结构内的导电材料的形成可以限于传输电信号所需的那些区域。