公开(公告)号：US11868621B2

公开(公告)日：2024-01-09

申请号：US17844174

申请日：2022-06-20

Applicant: Seagate Technology LLC

Inventor： Jon D. Trantham ,  Praveen Viraraghavan ,  John W. Dykes ,  Ian J. Gilbert ,  Sangita Shreedharan Kalarickal ,  Matthew J. Totin ,  Mohamad El-Batal ,  Darshana H. Mehta

IPC: G06F3/06 ,  G11C29/08

CPC classification number: G06F3/0616 ,  G06F3/0653 ,  G06F3/0679 ,  G11C29/08

Abstract: A data storage system can employ a read destructive memory configured with multiple levels. A non-volatile memory unit can be programmed with a first logical state in response to a first write voltage of a first hysteresis loop by a write controller prior to being programmed to a second logical state in response to a second write voltage of the first hysteresis loop, as directed by the write controller. The first and second logical states may be present concurrently in the non-volatile memory unit and subsequently read concurrently as the first logical state and the second logical state.

公开(公告)号：US20220350523A1

公开(公告)日：2022-11-03

申请号：US17730345

申请日：2022-04-27

Applicant: Seagate Technology LLC

Inventor： Jon D. Trantham ,  Praveen Viraraghavan ,  John W. Dykes ,  Ian J. Gilbert ,  Sangita Shreedharan Kalarickal ,  Matthew J. Totin ,  Mohamad El-Batal ,  Darshana H. Mehta

IPC: G06F3/06

Abstract: Apparatus and method for managing data in a processing system, such as but not limited to a data storage device such as a solid-state drive (SSD). A ferroelectric stack register memory has a first arrangement of ferroelectric memory cells (FMEs) of a first construction and a second arrangement of FMEs of a different, second construction arranged to provide respective cache lines for use by a controller, such as a programmable processor. A pointer mechanism is configured to provide pointers to point to each of the respective cache lines based on a time sequence of operation of the processor. Data sets can be migrated to the different arrangements by the controller as required based on the different operational characteristics of the respective FME constructions. The FMEs may be non-volatile and read-destructive. Refresh circuitry can be selectively enacted under different operational modes.

公开(公告)号：US20220343962A1

公开(公告)日：2022-10-27

申请号：US17726864

申请日：2022-04-22

Applicant: Seagate Technology LLC

Inventor： Jon D. Trantham ,  Praveen Viraraghavan ,  John W. Dykes ,  Ian J. Gilbert ,  Sangita Shreedharan Kalarickal ,  Matthew J. Totin ,  Mohamad El-Batal ,  Darshana H. Mehta

IPC: G11C11/22 ,  G11C17/12 ,  G11C7/10

Abstract: A system on chip (SOC) integrated circuit device having an incorporated ferroelectric memory configured to be selectively refreshed, or not, depending on different operational modes. The ferroelectric memory is formed of an array of ferroelectric memory elements (FMEs) characterized as non-volatile, read-destructive semiconductor memory cells each having at least one ferroelectric layer. The FMEs can include FeRAM, FeFET or FTJ constructions. A read/write circuit writes data to the FMEs and subsequently reads back data from the FMEs responsive to respective write and read signals supplied by a processor circuit of the SOC. A refresh circuit is selectively enabled in a first normal mode to refresh the FMEs after a read operation, and is selectively disabled in a second exception mode so that the FMEs are not refreshed after a read operation. The FMEs can be used as a main memory, a cache, a buffer, an OTP, a keystore, etc.

公开(公告)号：US11335376B1

公开(公告)日：2022-05-17

申请号：US17161523

申请日：2021-01-28

Applicant: Seagate Technology LLC

Inventor： Riyan Alex Mendonsa ,  Brett R. Herdendorf ,  Jon D. Trantham ,  Kevin Lee Van Pelt

IPC: G11B5/09 ,  G11B21/12 ,  G11B17/022 ,  G11B5/012

Abstract: A data storage device includes a primary storage media, a drive storage controller electrically coupled to media recording electronics and a controller-override mechanism. The controller-override mechanism is selectively controllable by a user to override control actions of the drive storage controller to prevent the drive storage controller from altering the primary storage media at a time when the storage device is otherwise configured for nominal data storage operations.

公开(公告)号：US10996900B2

公开(公告)日：2021-05-04

申请号：US16284687

申请日：2019-02-25

Applicant: Seagate Technology LLC

Inventor： Riyan A. Mendonsa ,  Brett R. Herdendorf ,  Jon D. Trantham

IPC: G06F3/06 ,  G11B5/55

Abstract: An implementation of a system disclosed herein includes a control board including multiple cartridge slots and hardware for coupling each of the multiple cartridge slots to an associated storage cartridge. The system further includes multiple voice coil motor (VCM) actuator components mounted to the control board, each one of the multiple VCM actuator configured to contribute to an electromagnetic interaction that drives movement of an actuator arm within a storage cartridge coupled to one of the multiple cartridge slots.

公开(公告)号：US20210109971A1

公开(公告)日：2021-04-15

申请号：US16597911

申请日：2019-10-10

Applicant: Seagate Technology LLC

Inventor： Lijuan Zhong ,  Krishnan Subramanian ,  Mehmet Fatih Erden ,  Jon D. Trantham

IPC: G06F16/901 ,  G06N3/08

Abstract: Features are detected from a sensor signal via a deep-learning network or other feature engineering methods in an edge processing node. Machine-learned metadata is created that describes the features, and a hash is created with the machine-learned metadata. The sensor signal is stored as a content object at the edge processing node, the object being keyed with the hash at, the edge processing node.

公开(公告)号：US10861496B1

公开(公告)日：2020-12-08

申请号：US16451809

申请日：2019-06-25

Applicant: Seagate Technology LLC

Inventor： Riyan Alex Mendonsa ,  Jon D. Trantham

IPC: G11B33/00 ,  G11B20/10 ,  G11B5/02 ,  G06F3/06

Abstract: A system includes a system-on-a-chip integrated circuit and a preamplifier integrated circuit. The system-on-a-chip integrated circuit includes an interface configured to receive an analog sensor signal and a read/write channel configured to digitize the analog sensor signal. The preamplifier integrated circuit is communicatively coupled to the system-on-a-chip integrated circuit and is configured to amplify the analog sensor signal.

公开(公告)号：US10818318B2

公开(公告)日：2020-10-27

申请号：US16358255

申请日：2019-03-19

Applicant: Seagate Technology LLC

Inventor： Brett R. Herdendorf ,  Jon D. Trantham ,  Anil J. Reddy ,  Riyan Alex Mendonsa ,  Krishnan Subramanian

IPC: G11B15/68 ,  G11B20/10

Abstract: A data storage library includes a number of storage cartridges arranged in a rack accessed by a actuated media player. The actuated media player is adapted to move along a plane relative to a fixed subset of the storage cartridges in the rack to and to selectively couple to each storage cartridge of the fixed subset to facilitate selective read/write access.

公开(公告)号：US10802853B2

公开(公告)日：2020-10-13

申请号：US15378983

申请日：2016-12-14

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Jon D. Trantham ,  Robert John Warmka ,  Chiaming Yang ,  David B. Anderson ,  Bryan David Wyatt

IPC: G06F9/455 ,  G06F8/40 ,  G06F8/61 ,  G06F9/445

Abstract: A data storage drive that includes a data storage medium and drive control circuit communicatively coupled to the data storage medium. The data storage drive also includes embedded applet management circuitry that executes an application, installed in the data storage drive as one or more key-value objects, within a controlled environment of the data storage drive.

公开(公告)号：US10408674B2

公开(公告)日：2019-09-10

申请号：US16352243

申请日：2019-03-13

Applicant: Seagate Technology LLC

Inventor： James Dillon Kiely ,  John Charles Duda ,  Patrick Carl Fletcher ,  Andrei Dorobantu ,  Jon D. Trantham

IPC: G01J1/42 ,  G01K7/16

Abstract: An apparatus comprises a light source configured to generate light, and a modulator coupled to the light source and configured to modulate the light above a predetermined frequency. A slider is configured for heat-assisted magnetic recording and to receive the modulated light. A resistive sensor is integral to the slider and subject to heating by absorption of electromagnetic radiation and conduction of heat. Measuring circuitry is coupled to the resistive sensor and configured to measure a response of the resistive sensor due to absorbed electromagnetic radiation and not from the heat conduction. The measuring circuitry may further be configured to determine output optical power of the light source using the measured resistive sensor response.