公开(公告)号：US11756977B2

公开(公告)日：2023-09-12

申请号：US16014359

申请日：2018-06-21

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter Gambino ,  Rick Jerome ,  David T. Price

IPC: H01L27/146 ,  H01L23/532

CPC classification number: H01L27/14636 ,  H01L23/53266 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/1464

Abstract: Implementations of image sensor devices may include a through-silicon-via (TSV) formed in a backside of an image sensor device and extending through a material of a die to a metal landing pad. The metal landing pad may be within a contact layer. The devices may include a TSV edge seal ring surrounding a portion of the TSV in the contact layer and extending from a first surface of the contact layer into the contact layer to a depth coextensive with a depth of the TSV.

公开(公告)号：US10431614B2

公开(公告)日：2019-10-01

申请号：US15421505

申请日：2017-02-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter Gambino ,  Kyle Thomas ,  David T. Price ,  Rusty Winzenread ,  Bruce Greenwood

IPC: H01L27/146

Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

公开(公告)号：US12080739B2

公开(公告)日：2024-09-03

申请号：US17029682

申请日：2020-09-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Manuel H. Innocent ,  Tomas Geurts ,  David T. Price

IPC: H01L27/146

CPC classification number: H01L27/14623 ,  H01L27/1461 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14689

Abstract: Implementations of a semiconductor device may include a photodiode included in a second epitaxial layer of a semiconductor substrate; light shield coupled over the photodiode; and a first epitaxial layer located in one or more openings in the light shield. The first epitaxial layer and the second epitaxial layer may form a single crystal.

公开(公告)号：US11961859B2

公开(公告)日：2024-04-16

申请号：US18305959

申请日：2023-04-24

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter Gambino ,  Kyle Thomas ,  David T. Price ,  Rusty Winzenread ,  Bruce Greenwood

IPC: H01L27/146

CPC classification number: H01L27/14618 ,  H01L27/14634 ,  H01L27/14636

Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

公开(公告)号：US11506687B2

公开(公告)日：2022-11-22

申请号：US17011027

申请日：2020-09-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Kevin Alexander Stewart ,  Martin Kejhar ,  Radim Mlcousek ,  Arash Elhami Khorasani ,  David T. Price ,  Mark Griswold

IPC: G01R15/14 ,  G01R19/00 ,  H01L27/06 ,  H01L49/02 ,  H01L29/808

Abstract: In one embodiment, a method of forming a semiconductor device may include forming a sense resistor to receive a high voltage signal and form a sense signal that is representative of the high voltage signal. An embodiment of the sense resistor may optionally be formed overlying a polysilicon resistor. The method may also have an embodiment that may include forming a plurality of capacitors in parallel to portions of the sense resistor wherein the plurality of capacitors are connected together in series.

公开(公告)号：US11075148B2

公开(公告)日：2021-07-27

申请号：US16675525

申请日：2019-11-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter Gambino ,  David T. Price ,  Jeffery A. Neuls ,  Dean E. Probst ,  Santosh Menon ,  Peter A. Burke ,  Bigildis Dosdos

IPC: H01L23/00 ,  H01L23/495 ,  H01L25/00 ,  H01L25/11

Abstract: A stacked assembly of semiconductor devices includes a mounting pad covering a first portion of a low-side semiconductor device, and a contact layer covering a second portion of the low-side semiconductor device. A first mounting clip electrically connected to the contact layer has a supporting portion joining the first mounting clip to a first lead frame portion. A second mounting clip attached to the mounting pad has a supporting portion joining the second mounting clip to a second lead frame portion. A high-side semiconductor device has a first terminal electrically connected to the first mounting clip and thereby to the contact layer, and a second terminal electrically connected to the second mounting clip.

公开(公告)号：US10403659B2

公开(公告)日：2019-09-03

申请号：US16116634

申请日：2018-08-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter Gambino ,  Angel Rodriguez ,  David T. Price ,  Jeffery Allen Neuls ,  Kenneth Andrew Bates ,  Rick Mauritzson

IPC: H01L27/146 ,  H01L27/06

Abstract: Implementations of image sensors may include a first die including an image sensor array and a first plurality of interconnects where the image sensor array includes a plurality of photodiodes and a plurality of transfer gates. The image sensor array may also include a second die including a second plurality of interconnects and a plurality of capacitors, each capacitor selected from the group consisting of deep trench capacitors, metal-insulator-metal (MIM) capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and 3D stacked capacitors. The first die may be coupled to the second die through the first plurality of interconnects and through the second plurality of interconnects. No more than eight photodiodes of the plurality of photodiodes of the first die may be electrically coupled with no more than four capacitors of the plurality of capacitors.

公开(公告)号：US09570494B1

公开(公告)日：2017-02-14

申请号：US14869490

申请日：2015-09-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Rick Jerome ,  David T. Price ,  Sungkwon C. Hong ,  Gordon M. Grivna

IPC: H01L21/00 ,  H01L27/146

CPC classification number: H01L27/1464 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/14605 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14683 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14689

Abstract: In one embodiment, a method for forming a backside illuminated image sensor includes providing a region of semiconductor material having a first major surface and a second major surface configured to receive incident light. A pixel structure is formed within the region of semiconductor material adjacent the first major surface. Thereafter, a trench structure comprising a metal material is formed extending through the region of semiconductor material. A first surface of the trench structure is adjacent the first major surface of the region of semiconductor material and a second surface adjoining the second major surface of the region of semiconductor material. A first contact structure is electrically connected to one surface of the conductive trench structure and a second contact structure is electrically connected to an opposing second surface.

Abstract translation: 在一个实施例中，用于形成背面照射的图像传感器的方法包括提供具有第一主表面的半导体材料区域和被配置为接收入射光的第二主表面。 像素结构形成在与第一主表面相邻的半导体材料的区域内。 此后，形成延伸穿过半导体材料区域的包括金属材料的沟槽结构。 沟槽结构的第一表面邻近半导体材料区域的第一主表面，邻接半导体材料区域的第二主表面的第二表面。 第一接触结构电连接到导电沟槽结构的一个表面，并且第二接触结构电连接到相对的第二表面。

公开(公告)号：US12211865B2

公开(公告)日：2025-01-28

申请号：US18586731

申请日：2024-02-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter Gambino ,  Kyle Thomas ,  David T. Price ,  Rusty Winzenread ,  Bruce Greenwood

IPC: H01L27/146

Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

公开(公告)号：US12034025B2

公开(公告)日：2024-07-09

申请号：US17302836

申请日：2021-05-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter Gambino ,  David T. Price ,  Marc Allen Sulfridge ,  Richard Mauritzson ,  Michael Gerard Keyes ,  Ryan Rettmann ,  Kevin Mcstay

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14603 ,  H01L27/14623 ,  H01L27/1464

Abstract: An imaging device may include single-photon avalanche diodes (SPADs). To mitigate crosstalk, isolation structures may be formed around each SPAD. The isolation structures may include front side deep trench isolation structures that extend partially or fully through a semiconductor substrate for the SPADs. The isolation structures may include a metal filler such as tungsten that absorbs photons. The isolation structures may include a p-type doped semiconductor liner to mitigate dark current. The isolation structures may include a buffer layer such as silicon dioxide that is interposed between the metal filler and the p-type doped semiconductor liner. The isolation structures may have a tapered portion or may be formed in two steps such that the isolation structures have different portions with different properties. An additional filler such as polysilicon or borophosphosilicate glass may be included in some of the isolation structures in addition to the metal filler.