公开(公告)号：US09431344B2

公开(公告)日：2016-08-30

申请号：US13941684

申请日：2013-07-15

Applicant: SK hynix Inc.

Inventor： Ki Hong Lee ,  Seung Ho Pyi ,  Jin Ho Bin

IPC: H01L23/532 ,  H01L21/764 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L23/53238 ,  H01L21/764 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53266 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11563 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device may include pillars and a plurality of conductive layers being stacked while surrounding the pillars and including a plurality of first regions including non-conductive material layers and a plurality of second regions including conductive material layers, wherein the first regions and the second regions are alternately arranged.

Abstract translation: 半导体器件可以包括柱状物和多个导电层，其围绕柱状物堆叠并且包括包括非导电材料层的多个第一区域和包括导电材料层的多个第二区域，其中第一区域和第二区域 交替排列。

公开(公告)号：US09202870B2

公开(公告)日：2015-12-01

申请号：US14741097

申请日：2015-06-16

Applicant: SK hynix Inc.

Inventor： Ki Hong Lee ,  Seung Ho Pyi ,  Jin Ho Bin

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/1054 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: A semiconductor device includes first conductive layers and first interlayer insulating layers stacked alternately with each other, at least one second conductive layer and at least one second interlayer insulating layer formed on the first conductive layers and the first interlayer insulating layers and stacked alternately with each other, a first semiconductor layer passing through the first conductive layers and the first interlayer insulating layers and including polysilicon, and a second semiconductor layer coupled to the first semiconductor layer and passing through the at least one second conductive layer the at least one second interlayer insulating layer, wherein the second semiconductor layer includes silicon germanium.

Abstract translation: 半导体器件包括彼此交替堆叠的第一导电层和第一层间绝缘层，形成在第一导电层和第一层间绝缘层上的至少一个第二导电层和至少一个第二层间绝缘层，并且彼此交替堆叠 穿过所述第一导电层和所述第一层间绝缘层并且包括多晶硅的第一半导体层，以及耦合到所述第一半导体层并且穿过所述至少一个第二导电层的所述至少一个第二层间绝缘层的第二半导体层 ，其中所述第二半导体层包括硅锗。

公开(公告)号：US09640550B2

公开(公告)日：2017-05-02

申请号：US15264349

申请日：2016-09-13

Applicant: SK hynix Inc.

Inventor： Ki Hong Lee ,  Seung Ho Pyi ,  Jin Ho Bin

IPC: H01L21/336 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11553 ,  H01L27/11556 ,  H01L21/768 ,  H01L27/11573 ,  H01L27/11575

CPC classification number: H01L27/11582 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578

Abstract: A semiconductor device includes a semiconductor pattern; conductive layers each including a first portion through which the semiconductor pattern passes and a second portion having a thickness greater than the first portion, wherein the first portion of each conductive layer includes a first barrier pattern surrounding the semiconductor pattern and a material pattern, which is formed in the first barrier pattern and has an etch selectivity with respect to the first barrier pattern, and the second portion of each conductive layer includes a conductive pattern; and contact plugs connected to the second portion of each of the conductive layers.

公开(公告)号：US09472567B2

公开(公告)日：2016-10-18

申请号：US14480207

申请日：2014-09-08

Applicant: SK hynix Inc.

Inventor： Ki Hong Lee ,  Seung Ho Pyi ,  Jin Ho Bin

IPC: H01L29/792 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578

Abstract: A semiconductor device includes a semiconductor pattern; conductive layers each including a first portion through which the semiconductor pattern passes and a second portion having a thickness greater than the first portion, wherein the first portion of each conductive layer includes a first barrier pattern surrounding the semiconductor pattern and a material pattern, which is formed in the first barrier pattern and has an etch selectivity with respect to the first barrier pattern, and the second portion of each conductive layer includes a conductive pattern; and contact plugs connected to the second portion of each of the conductive layers.

Abstract translation: 半导体器件包括半导体图案; 导电层各自包括半导体图案通过的第一部分和具有大于第一部分的厚度的第二部分，其中每个导电层的第一部分包括围绕半导体图案的第一阻挡图案和材料图案，其为 形成在第一阻挡图案中，并且具有相对于第一阻挡图案的蚀刻选择性，并且每个导电层的第二部分包括导电图案; 以及连接到每个导电层的第二部分的接触插塞。

公开(公告)号：US09324824B2

公开(公告)日：2016-04-26

申请号：US14324953

申请日：2014-07-07

Applicant: SK hynix Inc.

Inventor： Ki Hong Lee ,  Jin Ho Bin ,  Soo Jin Kim ,  Seung Ho Pyi

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/49 ,  H01L29/06 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L21/76847 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76879 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/0649 ,  H01L29/4941 ,  H01L29/495 ,  H01L29/4991 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7828

Abstract: A semiconductor device including a central region, side regions located in both sides of the central region, and conductive layers including a first barrier pattern formed in the central region, a material pattern formed in the first barrier pattern and having an etch selectivity with respect to the first barrier pattern, and a second barrier pattern formed in the material pattern; and insulating layers alternately stacked with the conductive layers.

Abstract translation: 一种半导体器件，包括中心区域，位于中心区域两侧的侧面区域和形成在中心区域中的包括第一势垒图案的导电层，形成在第一阻挡图案中的材料图案，并且具有相对于 第一阻挡图案和形成在材料图案中的第二阻挡图案; 以及与导电层交替堆叠的绝缘层。

公开(公告)号：US09087735B2

公开(公告)日：2015-07-21

申请号：US13828109

申请日：2013-03-14

Applicant: SK hynix Inc.

Inventor： Ki Hong Lee ,  Seung Ho Pyi ,  Jin Ho Bin

IPC: H01L29/04 ,  H01L29/10 ,  H01L31/036 ,  H01L27/115

CPC classification number: H01L29/1054 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: A semiconductor device includes first conductive layers and first interlayer insulating layers stacked alternately with each other, at least one second conductive layer and at least one second interlayer insulating layer formed on the first conductive layers and the first interlayer insulating layers and stacked alternately with each other, a first semiconductor layer passing through the first conductive layers and the first interlayer insulating layers and including polysilicon, and a second semiconductor layer coupled to the first semiconductor layer and passing through the at least one second conductive layer the at least one second interlayer insulating layer, wherein the second semiconductor layer includes silicon germanium.

公开(公告)号：US11239251B2

公开(公告)日：2022-02-01

申请号：US16855766

申请日：2020-04-22

Applicant: SK hynix Inc.

Inventor： Hye Hyeon Byeon ,  Il Young Kwon ,  Jin Ho Bin

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/3115 ,  H01L21/02 ,  H01L21/311

Abstract: A method of manufacturing a non-volatile memory device includes forming a gate insulation layer on a semiconductor substrate having a source layer. The method also includes forming a silicon nitride layer having a buffer-treated upper surface on the gate insulation layer, wherein the buffer-treated upper surface of the silicon nitride layer has a hardness higher than a hardness of the silicon nitride layer. The method further includes forming a silicon oxide layer on the buffer-treated upper surface of the silicon nitride layer. The method additionally includes alternately forming additional silicon nitride layers and additional silicon oxide layers on the silicon oxide layer to form a stack structure.

公开(公告)号：US10811429B2

公开(公告)日：2020-10-20

申请号：US16177166

申请日：2018-10-31

Applicant: SK hynix Inc.

Inventor： Jin Ho Bin ,  Il Young Kwon ,  Il Do Kim

IPC: H01L27/11582 ,  H01L29/10 ,  H01L21/768 ,  H01L27/11556

Abstract: A semiconductor device includes a stack structure including conductive layers and insulating layers, which are alternately stacked; an opening including a first opening penetrating the stack structure and second openings protruding from the first opening; and a channel layer including channel regions located in the second openings and impurity regions located in the first opening, the impurity regions having an impurity concentration higher than that of the channel regions.

公开(公告)号：US11322517B2

公开(公告)日：2022-05-03

申请号：US17022215

申请日：2020-09-16

Applicant: SK hynix Inc.

Inventor： Jin Ho Bin ,  Il Young Kwon ,  Il Do Kim

IPC: H01L27/11582 ,  H01L29/10 ,  H01L21/768 ,  H01L27/11556

Abstract: A semiconductor device includes a stack structure including conductive layers and insulating layers, which are alternately stacked; an opening including a first opening penetrating the stack structure and second openings protruding from the first opening; and a channel layer including channel regions located in the second openings and impurity regions located in the first opening, the impurity regions having an impurity concentration higher than that of the channel regions.

公开(公告)号：US09780036B2

公开(公告)日：2017-10-03

申请号：US15225457

申请日：2016-08-01

Applicant: SK hynix Inc.

Inventor： Ki Hong Lee ,  Seung Ho Pyi ,  Jin Ho Bin

IPC: H01L23/532 ,  H01L29/792 ,  H01L29/66 ,  H01L29/788 ,  H01L21/764 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11517 ,  H01L27/11563 ,  H01L27/11519

CPC classification number: H01L23/53238 ,  H01L21/764 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53266 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11563 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device may include pillars and a plurality of conductive layers being stacked while surrounding the pillars and including a plurality of first regions including non-conductive material layers and a plurality of second regions including conductive material layers, wherein the first regions and the second regions are alternately arranged.