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公开(公告)号：US11996865B2
公开(公告)日：2024-05-28
申请号：US18185163
申请日：2023-03-16
Applicant: SK hynix Inc.
Inventor： Kyoung Lae Cho , Soo Jin Kim , Naveen Kumar , Aman Bhatia , Yi-Min Lin , Chenrong Xiong , Fan Zhang , Yu Cai , Abhiram Prabahkar
CPC classification number: H03M13/3707 , G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F11/1048 , G06F11/1076 , H03M13/1108 , H03M13/1111
Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
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公开(公告)号：US10523245B2
公开(公告)日：2019-12-31
申请号：US15460155
申请日：2017-03-15
Applicant: SK Hynix Inc.
Inventor： Naveen Kumar , Aman Bhatia , Yi-Min Lin
Abstract: A memory device includes a memory array, a processor, and a decoding apparatus. The processor is coupled to the memory array and configured to read encoded data from the memory array. The encoded data includes a plurality of data blocks and each data block is included in two or more data codewords. Further, data codewords belonging to a same pair of data codewords share a common data block. The decoding apparatus is configured to iteratively decode data codewords using hard decoding and soft decoding, and to correct stuck errors by identifying failed data blocks based on shared blocks between failed data codewords.
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公开(公告)号：US10326477B2
公开(公告)日：2019-06-18
申请号：US15379098
申请日：2016-12-14
Applicant: SK Hynix Inc.
Inventor： Naveen Kumar , Aman Bhatia , Yi-Min Lin
Abstract: Techniques are described for protecting miscorrection in a codeword. In one example, the techniques include obtaining a first set of data to be encoded using a product code comprising one or more constituent codes, and generating a second set of data by performing a miscorrection avoidance procedure on the first set of data. The miscorrection avoidance procedure decreases a probability of miscorrection at a decoder. The techniques further includes jointly encoding the first and the second set of data using an encoding procedure corresponding to the product code to generate at least one encoded codeword, and storing the encoded codeword in the memory.
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公开(公告)号：US20170310342A1
公开(公告)日：2017-10-26
申请号：US15453126
申请日：2017-03-08
Applicant: SK Hynix Inc.
Inventor： Johnson Yen , HongChich Chou , Yi-Min Lin
CPC classification number: H03M13/3715
Abstract: Techniques are described for codeword decoding. In an example, a system computes a checksum for a codeword based on the codeword and a parity check matrix. The system compares the checksum to thresholds. Each threshold is associated with a different decoder from a plurality of decoders available on the system. The system selects a decoder from the plurality of decoders. The decoder is selected based on the comparison of the checksum to the thresholds. The system decodes the codeword by using the selected decoder.
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公开(公告)号：US20170279467A1
公开(公告)日：2017-09-28
申请号：US15432255
申请日：2017-02-14
Applicant: SK Hynix Inc.
Inventor： Aman Bhatia , Naveen Kumar , Yi-Min Lin , Lingqi Zeng
CPC classification number: H03M13/2909 , H03M13/152 , H03M13/2918 , H03M13/2963 , H03M13/453
Abstract: Techniques are described for decoding a codeword. In one example, the techniques include obtaining a first message comprising reliability information corresponding to each bit in the first codeword, determining a plurality of least reliable bits in the first codeword, and generating a plurality of flipped messages by flipping one or more of the plurality of least reliable bits in the first codeword. A number of the plurality of least reliable bits is equal to a first parameter and a number of flipped bits in each of the plurality of flipped messages is less than or equal to a second parameter. The method further includes decoding one or more of the plurality of flipped messages using a hard decoder to generate one or more candidate codewords.
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Patent Agency Ranking
公开(公告)号：US20170264320A1
公开(公告)日：2017-09-14
申请号：US15433850
申请日：2017-02-15
Applicant: SK Hynix Inc.
Inventor： Yi-Min Lin , Aman Bhatia , Naveen Kumar , Johnson Yen
CPC classification number: H03M13/2963 , H03M13/152 , H03M13/1545 , H03M13/618 , H03M13/6516
Abstract: An apparatus for decoding is disclosed. The apparatus includes a memory and a processor coupled to the memory. The processor is configured to obtain a first codeword comprising one or more information bits and one or more parity bits, obtain a first parameter corresponding to a code rate of the first codeword, and decode the first codeword using a multi-rate decoder to generate a decoded codeword. The multi rate decoder performs a code reconstruction procedure on the first codeword to generate a reconstructed codeword, and decodes the reconstructed codeword. The processor is further configured to output the decoded codeword.
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公开(公告)号：US11611359B2
公开(公告)日：2023-03-21
申请号：US16987977
申请日：2020-08-07
Applicant: SK hynix Inc.
Inventor： Kyoung Lae Cho , Soo Jin Kim , Naveen Kumar , Aman Bhatia , Yi-Min Lin , Chenrong Xiong , Fan Zhang , Yu Cai , Abhiram Prabahkar
Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
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8.发明授权公开(公告)号：US10439649B2
公开(公告)日：2019-10-08
申请号：US15411773
申请日：2017-01-20
Applicant: SK Hynix Inc.
Inventor： Naveen Kumar , Yi-Min Lin , Aman Bhatia
Abstract: A memory device includes a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform coarse decoding and fine decoding. In coarse decoding, the decoder decodes in parallel two or more codewords, which share a common block of bits, to determine error information. Next, the decoder corrects errors in a first codeword based on the error information. Then, it is determined if the shared common block of data bits is corrected. If the shared common data block is updated, then error correction based on the error information is prohibited in codewords sharing the common block of data bits with the first codeword. In fine decoding, a single codeword is decoded at a time for error correction.
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公开(公告)号：US10090862B2
公开(公告)日：2018-10-02
申请号：US15433857
申请日：2017-02-15
Applicant: SK Hynix Inc.
Inventor： Yi-Min Lin , Aman Bhatia , Naveen Kumar , Johnson Yen
Abstract: An apparatus for decoding a TPC codeword is disclosed. The apparatus includes a memory and a processor coupled to the memory. The processor is configured to receive a first set of soft information corresponding to the TPC codeword. The TPC codeword includes at least one codeword corresponding to each of first, second, and third dimensions. The processor is further configured to iteratively perform a first soft decoding procedure on the at least one codeword corresponding to the first dimension to generate a first candidate codeword and upon determining that the first candidate codeword is not a correct codeword, and perform a second decoding procedure on the at least one codeword corresponding to the third dimension to generate a second candidate codeword. The second decoding procedure generates a second set of soft information to be used at a later iteration of the first decoding procedure.
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公开(公告)号：US20170279466A1
公开(公告)日：2017-09-28
申请号：US15433857
申请日：2017-02-15
Applicant: SK Hynix Inc.
Inventor： Yi-Min Lin , Aman Bhatia , Naveen Kumar , Johnson Yen
CPC classification number: H03M13/2963 , H03M13/152 , H03M13/2909 , H03M13/2918 , H03M13/3944 , H03M13/453 , H03M13/6502
Abstract: An apparatus for decoding a TPC codeword is disclosed. The apparatus includes a memory and a processor coupled to the memory. The processor is configured to receive a first set of soft information corresponding to the TPC codeword. The TPC codeword includes at least one codeword corresponding to each of first, second, and third dimensions. The processor is further configured to iteratively perform a first soft decoding procedure on the at least one codeword corresponding to the first dimension to generate a first candidate codeword and upon determining that the first candidate codeword is not a correct codeword, and perform a second decoding procedure on the at least one codeword corresponding to the third dimension to generate a second candidate codeword. The second decoding procedure generates a second set of soft information to be used at a later iteration of the first decoding procedure.
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