公开(公告)号：US20170199684A1

公开(公告)日：2017-07-13

申请号：US14994065

申请日：2016-01-12

Applicant: SMART Modular Technologies, Inc.

Inventor： Amir Alavi

IPC: G06F3/06 ,  G06F1/32 ,  G06F13/28

CPC classification number: G06F1/3225 ,  G06F11/07 ,  G06F13/28

Abstract: An memory management system with backup system, and a method of operation of a memory management system with backup system thereof, including: a memory module controller for detecting a power failure condition, the memory module controller including a nonvolatile memory controller; a compression controller integrated within the nonvolatile memory controller for receiving a data block from volatile memory; a compression engine within the compression controller for compressing the data block to form a compressed data block; and a sequencer for writing the compressed data block to nonvolatile memory.

公开(公告)号：US20180095661A1

公开(公告)日：2018-04-05

申请号：US15285305

申请日：2016-10-04

Applicant: SMART Modular Technologies, Inc.

Inventor： Rajesh Ananthanarayanan ,  Jinying Shen ,  Amir Alavi

IPC: G06F3/06 ,  G06F12/06

CPC classification number: G06F3/061 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0673

Abstract: Approaches, techniques, and mechanisms are disclosed for improving the performance of memory controllers for memory devices. A system may have a memory controller that interfaces with a memory device to store or retrieve information. When the system needs to retrieve information from the memory device, the memory controller sends an address and a command to instruct the memory device to read the information stored at the address. The memory device reads the information, and after a specific amount of time, the memory device sends the information to the memory controller. According to an embodiment, “dummy” data is sent first prior to the availability of the data read out of the memory devices, while waiting for the requested data to be accessed, and then the actual data is sent immediately following the dummy data. According to an embodiment, a geometry of a memory device has only one column of memory cells that are used to store information. The memory device with only one column in an embodiment does not require decoding of a column address. As such, the read latency of the memory device is significantly reduced.

公开(公告)号：US10338821B2

公开(公告)日：2019-07-02

申请号：US15285305

申请日：2016-10-04

Applicant: SMART Modular Technologies, Inc.

Inventor： Rajesh Ananthanarayanan ,  Jinying Shen ,  Amir Alavi

IPC: G06F3/06

Abstract: Approaches, techniques, and mechanisms are disclosed for improving the performance of memory controllers for memory devices. A system may have a memory controller that interfaces with a memory device to store or retrieve information. When the system needs to retrieve information from the memory device, the memory controller sends an address and a command to instruct the memory device to read the information stored at the address. The memory device reads the information, and after a specific amount of time, the memory device sends the information to the memory controller. According to an embodiment, “dummy” data is sent first prior to the availability of the data read out of the memory devices, while waiting for the requested data to be accessed, and then the actual data is sent immediately following the dummy data. According to an embodiment, a geometry of a memory device has only one column of memory cells that are used to store information. The memory device with only one column in an embodiment does not require decoding of a column address. As such, the read latency of the memory device is significantly reduced.