公开(公告)号：US08975980B2

公开(公告)日：2015-03-10

申请号：US14018282

申请日：2013-09-04

Applicant: STATS ChipPAC, Ltd.

Inventor： Kai Liu ,  Robert C. Frye ,  Yaojian Lin

IPC: H01P3/08 ,  H01F19/00 ,  H03H7/42 ,  H03H7/09 ,  H03H7/01 ,  H01L49/02

CPC classification number: H03H7/422 ,  H01L28/10 ,  H03H7/09 ,  H03H7/1766 ,  H03H7/42

Abstract: A band-pass filter has a plurality of frequency band channels each including a first inductor having a first terminal coupled to a first balanced port and a second terminal coupled to a second balanced port. A first capacitor is coupled between the first and second terminals of the first inductor. A second inductor has a first terminal coupled to a first unbalanced port and a second terminal coupled to a second unbalanced port. The second inductor is disposed within a first distance of the first inductor to induce magnetic coupling. A second capacitor is coupled between the first and second terminals of the second inductor. A third inductor is disposed within a second distance of the first inductor and within a third distance of the second inductor to induce magnetic coupling. A second capacitor is coupled between first and second terminals of the third inductor.

Abstract translation: 带通滤波器具有多个频带信道，每个频带信道包括具有耦合到第一平衡端口的第一端子的第一电感器和耦合到第二平衡端口的第二端子。 第一电容器耦合在第一电感器的第一和第二端子之间。 第二电感器具有耦合到第一不平衡端口的第一端子和耦合到第二不平衡端口的第二端子。 第二电感器设置在第一电感器的第一距离内以引起磁耦合。 第二电容器耦合在第二电感器的第一和第二端子之间。 第三电感器设置在第一电感器的第二距离内并且在第二电感器的第三距离内，以引起磁耦合。 第二电容器耦合在第三电感器的第一和第二端子之间。

公开(公告)号：US09484334B2

公开(公告)日：2016-11-01

申请号：US13716799

申请日：2012-12-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Robert C. Frye ,  Kai Liu

IPC: H03H7/42 ,  H01L27/01 ,  H01P5/10 ,  H03H7/48 ,  H01L21/70 ,  H05K1/02 ,  H03H5/00 ,  H05K1/16

CPC classification number: H01L27/01 ,  H01L21/70 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01P5/10 ,  H03H7/48 ,  H05K1/0233 ,  H05K1/0239 ,  H05K1/0243 ,  H05K1/025 ,  H05K1/165 ,  H05K2201/09245 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has a substrate and RF coupler formed over the substrate. The RF coupler has a first conductive trace with a first end coupled to a first terminal of the semiconductor device, and a second conductive trace with a first end coupled to a second terminal of the semiconductor device. The first conductive trace is placed in proximity to a first portion of the second conductive trace. An integrated passive device is formed over the substrate. A second portion of the second conductive trace operates as a circuit component of the integrated passive device. The integrated passive device can be a balun or low-pass filter. The RF coupler also has a first capacitor coupled to the first terminal of the semiconductor device, and second capacitor coupled to a third terminal of the semiconductor device for higher directivity. The second conductive trace is wound to exhibit an inductive property.

公开(公告)号：US09171797B2

公开(公告)日：2015-10-27

申请号：US13910786

申请日：2013-06-05

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Robert C. Frye

IPC: H01L23/52 ,  H01L23/48 ,  H01L21/50 ,  H01L21/48 ,  H01L21/683 ,  H01L23/538 ,  H01L23/64 ,  H01L25/16 ,  H05K1/16 ,  H01L21/56 ,  H01L23/31 ,  H05K3/20 ,  H05K3/28 ,  H05K3/46

CPC classification number: H01L23/52 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/64 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/16 ,  H05K3/20 ,  H05K3/284 ,  H05K3/4644 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A semiconductor device has a substrate, first passivation layer formed over the substrate, and integrated passive device formed over the substrate. The integrated passive device can include an inductor, capacitor, and resistor. A second passivation layer is formed over the integrated passive device. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive device. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive device. A metal layer can be formed over the molding compound or first passivation layer for shielding.

Abstract translation: 半导体器件具有衬底，形成在衬底上的第一钝化层和形成在衬底上的集成无源器件。 集成无源器件可以包括电感器，电容器和电阻器。 在该集成无源器件上形成第二钝化层。 系统组件被安装到第二钝化层并电连接到第二导电层。 在整合的无源器件上形成模具化合物。 模具化合物的热膨胀系数近似等于系统组分的热膨胀系数。 去除衬底。 将一个开口蚀刻到第一钝化层中，并且将焊料凸块沉积在第一钝化层中的开口上，以电连接到集成的无源器件。 可以在模制化合物或第一钝化层上形成金属层以进行屏蔽。

公开(公告)号：US20130264716A1

公开(公告)日：2013-10-10

申请号：US13910786

申请日：2013-06-05

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Robert C. Frye

IPC: H01L23/52 ,  H01L21/56

CPC classification number: H01L23/52 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/64 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/16 ,  H05K3/20 ,  H05K3/284 ,  H05K3/4644 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A semiconductor device has a substrate, first passivation layer formed over the substrate, and integrated passive device formed over the substrate. The integrated passive device can include an inductor, capacitor, and resistor. A second passivation layer is formed over the integrated passive device. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive device. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive device. A metal layer can be formed over the molding compound or first passivation layer for shielding.

Abstract translation: 半导体器件具有衬底，形成在衬底上的第一钝化层和形成在衬底上的集成无源器件。 集成无源器件可以包括电感器，电容器和电阻器。 在该集成无源器件上形成第二钝化层。 系统组件被安装到第二钝化层并电连接到第二导电层。 在整合的无源器件上形成模具化合物。 模具化合物的热膨胀系数近似等于系统组分的热膨胀系数。 去除衬底。 将一个开口蚀刻到第一钝化层中，并且将焊料凸块沉积在第一钝化层中的开口上，以电连接到集成的无源器件。 可以在模制化合物或第一钝化层上形成金属层以进行屏蔽。

公开(公告)号：US20130171800A1

公开(公告)日：2013-07-04

申请号：US13765478

申请日：2013-02-12

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Robert C. Frye

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105

Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.

Abstract translation: 一种制造半导体器件的方法包括提供具有设置在基板的顶表面上的第一导电层的基板。 在基板和第一导电层上形成高电阻率层。 介电层沉积在衬底，第一导电层和高电阻率层上。 介电层，高电阻率层和第一导电层的一部分形成电容器叠层。 在电介质层上形成第一钝化层。 在电容器堆叠和第一钝化层的一部分上形成第二导电层。 在电介质层中蚀刻第一开口以暴露高电阻率层的表面。 在电介质层中的第一开口和第一钝化层的一部分上沉积第三和第四导电层。

公开(公告)号：US08703548B2

公开(公告)日：2014-04-22

申请号：US13765478

申请日：2013-02-12

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Robert C. Frye

IPC: H01L21/339

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105

Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.

Abstract translation: 一种制造半导体器件的方法包括提供具有设置在基板的顶表面上的第一导电层的基板。 在基板和第一导电层上形成高电阻率层。 介电层沉积在衬底，第一导电层和高电阻率层上。 介电层，高电阻率层和第一导电层的一部分形成电容器叠层。 在电介质层上形成第一钝化层。 在电容器堆叠和第一钝化层的一部分上形成第二导电层。 在电介质层中蚀刻第一开口以暴露高电阻率层的表面。 在电介质层中的第一开口和第一钝化层的一部分上沉积第三和第四导电层。

公开(公告)号：US20140002207A1

公开(公告)日：2014-01-02

申请号：US14018282

申请日：2013-09-04

Applicant: STATS ChipPAC, Ltd.

Inventor： Kai Liu ,  Robert C. Frye ,  Yaojian Lin

IPC: H03H7/42 ,  H01L49/02

CPC classification number: H03H7/422 ,  H01L28/10 ,  H03H7/09 ,  H03H7/1766 ,  H03H7/42

Abstract: A band-pass filter has a plurality of frequency band channels each including a first inductor having a first terminal coupled to a first balanced port and a second terminal coupled to a second balanced port. A first capacitor is coupled between the first and second terminals of the first inductor. A second inductor has a first terminal coupled to a first unbalanced port and a second terminal coupled to a second unbalanced port. The second inductor is disposed within a first distance of the first inductor to induce magnetic coupling. A second capacitor is coupled between the first and second terminals of the second inductor. A third inductor is disposed within a second distance of the first inductor and within a third distance of the second inductor to induce magnetic coupling. A second capacitor is coupled between first and second terminals of the third inductor.

Abstract translation: 带通滤波器具有多个频带信道，每个频带信道包括具有耦合到第一平衡端口的第一端子的第一电感器和耦合到第二平衡端口的第二端子。 第一电容器耦合在第一电感器的第一和第二端子之间。 第二电感器具有耦合到第一不平衡端口的第一端子和耦合到第二不平衡端口的第二端子。 第二电感器设置在第一电感器的第一距离内以引起磁耦合。 第二电容器耦合在第二电感器的第一和第二端子之间。 第三电感器设置在第一电感器的第二距离内并且在第二电感器的第三距离内，以引起磁耦合。 第二电容器耦合在第三电感器的第一和第二端子之间。

公开(公告)号：US20130099356A1

公开(公告)日：2013-04-25

申请号：US13716799

申请日：2012-12-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Robert C. Frye ,  Kai Liu

IPC: H01L27/01 ,  H01L21/70

CPC classification number: H01L27/01 ,  H01L21/70 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01P5/10 ,  H03H7/48 ,  H05K1/0233 ,  H05K1/0239 ,  H05K1/0243 ,  H05K1/025 ,  H05K1/165 ,  H05K2201/09245 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has a substrate and RF coupler formed over the substrate. The RF coupler has a first conductive trace with a first end coupled to a first terminal of the semiconductor device, and a second conductive trace with a first end coupled to a second terminal of the semiconductor device. The first conductive trace is placed in proximity to a first portion of the second conductive trace. An integrated passive device is formed over the substrate. A second portion of the second conductive trace operates as a circuit component of the integrated passive device. The integrated passive device can be a balun or low-pass filter. The RF coupler also has a first capacitor coupled to the first terminal of the semiconductor device, and second capacitor coupled to a third terminal of the semiconductor device for higher directivity. The second conductive trace is wound to exhibit an inductive property.

Abstract translation: 半导体器件具有在衬底上形成的衬底和RF耦合器。 RF耦合器具有第​​一导电迹线，其第一端耦合到半导体器件的第一端子，第二导电迹线具有耦合到半导体器件的第二端子的第一端。 第一导电迹线放置在第二导电迹线的第一部分附近。 在衬底上形成集成的无源器件。 第二导电迹线的第二部分用作集成无源器件的电路部件。 集成的无源器件可以是平衡 - 不平衡转换/低通滤波器。 RF耦合器还具有耦合到半导体器件的第一端子的第一电容器，并且耦合到半导体器件的第三端子的第二电容器用于更高的方向性。 第二导电迹线被卷绕以呈现感应特性。