公开(公告)号：US11462624B2

公开(公告)日：2022-10-04

申请号：US16230137

申请日：2018-12-21

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Samuel Menard

IPC: H01L29/00 ,  H01L29/47 ,  H01L29/73 ,  H01L29/747 ,  H01L29/74 ,  H01L29/732 ,  H01L29/417 ,  H01L29/45

Abstract: A vertical semiconductor triode includes a first layer of semiconductor material, the first layer including first and second surfaces, the first surface being in contact with a first electrode forming a Schottky contact.

公开(公告)号：US11362204B2

公开(公告)日：2022-06-14

申请号：US16706201

申请日：2019-12-06

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard ,  Lionel Jaouen

IPC: H01L29/74 ,  H01L29/749 ,  H01L29/06 ,  H01L29/08

Abstract: A thyristor is formed from a vertical stack of first, second, third, and fourth semiconductor regions of alternated conductivity types. The fourth semiconductor region is interrupted in a gate area of the thyristor. The fourth semiconductor region is further interrupted in a continuous corridor that extends longitudinally from the gate area towards an outer lateral edge of the fourth semiconductor region. A gate metal layer extends over the gate area of the thyristor. A cathode metal layer extends over the fourth semiconductor region but not over the continuous corridor.

公开(公告)号：US20170288044A1

公开(公告)日：2017-10-05

申请号：US15362919

申请日：2016-11-29

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard

IPC: H01L29/747 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/747 ,  H01L29/408 ,  H01L29/66386

Abstract: A vertical power component includes a doped silicon substrate of a first conductivity type. A local well of a second conductivity type extends from an upper surface of the substrate. A passivation structure coats a peripheral region of the upper surface side of the substrate surrounding the well. This passivation structure includes, on top of and in contact with the peripheral substrate region, a first region made of a first passivation material and a second region made of a second passivation material. The second region generates, in a surface region of the substrate in contact with said second region, a local increase of the concentration of majority carriers in the substrate.

公开(公告)号：US20160344384A1

公开(公告)日：2016-11-24

申请号：US14957984

申请日：2015-12-03

Applicant: STMicroelectronics (Tours) SAS

Inventor： Yannick Hague ,  Samuel Menard

IPC: H03K17/735

CPC classification number: H03K17/735 ,  H01L29/7408 ,  H01L29/7412 ,  H01L29/747 ,  H03K17/06 ,  H03K17/16 ,  H03K17/725 ,  H03K17/74 ,  H03K2017/066

Abstract: A bidirectional power switch includes first and second thyristors connected in antiparallel between first and second conduction terminals of the switch. The first thyristor is of an anode-gate thyristor, and the second thyristor is of a cathode-gate thyristor. The gates of the first and second thyristors are coupled to a same control terminal of the switch by respective dipole circuits. At least one of the dipole circuits is formed by at least one diode or at least one resistor.

Abstract translation: 双向功率开关包括在开关的第一和第二导通端之间反向并联连接的第一和第二晶闸管。 第一晶闸管是阳极闸晶闸管，第二晶闸管是阴极闸极晶闸管。 第一和第二晶闸管的栅极通过相应的偶极子电路耦合到开关的相同控制端子。 偶极电路中的至少一个由至少一个二极管或至少一个电阻器形成。

公开(公告)号：US09455253B2

公开(公告)日：2016-09-27

申请号：US14730826

申请日：2015-06-04

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard ,  Dalaf Ali

IPC: H01L27/08 ,  H01L23/528 ,  H01L29/747 ,  H01L29/08

CPC classification number: H01L27/0817 ,  H01L23/528 ,  H01L29/0834 ,  H01L29/747 ,  H01L2924/0002 ,  H01L2924/13033 ,  H01L2924/00

Abstract: A bidirectional switch formed in a substrate includes first and second main vertical thyristors in antiparallel connection. A third auxiliary vertical thyristor has a rear surface layer in common with the rear surface layer of the first thyristor. A peripheral region surrounds the thyristors and connects the rear surface layer to a layer of the same conductivity type of the third thyristor located on the other side of the substrate. A metallization connects the rear surfaces of the first and second thyristors. An insulating structure is located between the rear surface layer of the third thyristor and the metallization. The insulating structure extends under the periphery of the first thyristor. The insulating structure includes a region made of an insulating material and a complementary region made of a semiconductor material.

Abstract translation: 形成在衬底中的双向开关包括反并联连接的第一和第二主垂直晶闸管。 第三辅助垂直晶闸管具有与第一晶闸管的后表面层共同的后表面层。 周边区域围绕晶闸管并且将后表面层连接到位于基板另一侧上的与第三晶闸管相同的导电类型的层。 金属化连接第一和第二晶闸管的后表面。 绝缘结构位于第三晶闸管的后表面层与金属化之间。 绝缘结构在第一晶闸管的外围延伸。 绝缘结构包括由绝缘材料制成的区域和由半导体材料制成的互补区域。

公开(公告)号：US09070738B2

公开(公告)日：2015-06-30

申请号：US14494692

申请日：2014-09-24

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard

IPC: H01L29/74 ,  H01L29/16 ,  H01L29/66 ,  H01L21/02 ,  H01L21/322 ,  H01L29/08 ,  H01L21/306

CPC classification number: H01L29/74 ,  H01L21/2807 ,  H01L21/306 ,  H01L29/0692 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/102 ,  H01L29/32 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66363 ,  H01L29/66545 ,  H01L29/7408

Abstract: An SCR-type component of vertical structure has a main upper electrode formed on a silicon region of a first conductivity type which is formed in a silicon layer of a second conductivity type. The silicon region is interrupted in first areas where the material of the silicon layer comes into contact with the upper electrode, and is further interrupted in second areas filled with resistive porous silicon extending between the silicon layer and the main upper electrode.

Abstract translation: 垂直结构的SCR型分量具有形成在第二导电类型的硅层中的形成在第一导电类型的硅区上的主上电极。 在硅层的材料与上电极接触的第一区域中，硅区被中断，并且在硅层和主上电极之间延伸的第二区填充有电阻性多孔硅，进一步中断。

公开(公告)号：US20130320395A1

公开(公告)日：2013-12-05

申请号：US13901494

申请日：2013-05-23

Applicant: Universite Francois Rabelais ,  STMicroelectronics (Tours) SAS

Inventor： Samuel Menard ,  Gaël Gautier

IPC: H01L29/74

CPC classification number: H01L29/74 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0661 ,  H01L29/66386 ,  H01L29/747

Abstract: A vertical power component including: a silicon substrate of a first conductivity type; on the side of a lower surface of the substrate supporting a single electrode, a lower layer of the second conductivity type; and on the side of an upper surface of the substrate supporting a conduction electrode and a gate electrode, an upper region of the second conductivity type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer.

Abstract translation: 一种垂直功率分量，包括：第一导电类型的硅衬底; 在支撑单个电极的基板的下表面侧，具有第二导电类型的下层; 并且在支撑导电电极和栅电极的基板的上表面侧，具有第二导电类型的上部区域，其中，所述元件周边在下表面上包括穿入基板的多孔硅绝缘环 下降到比下层更深的深度。

公开(公告)号：US10707337B2

公开(公告)日：2020-07-07

申请号：US16052378

申请日：2018-08-01

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard

IPC: H01L29/74 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/747 ,  H01L29/08

Abstract: A one-way switch has a gate referenced to a main back side electrode. An N-type substrate includes a P-type anode layer covering a back side and a surrounding P-type wall. First and second P-type wells are formed on the front side of the N-type substrate. An N-type cathode region is located in the first P-type well. An N-type gate region is located in the second P-type well. A gate metallization covers both the N-type gate region and a portion of the second P-type well. The second P-type well is separated from the P-type wall by the N-type substrate except at a location of a P-type strip that is formed in the N-type substrate and connects a portion on one side of the second P-type well to an upper portion of said P-type wall.

公开(公告)号：US10069001B2

公开(公告)日：2018-09-04

申请号：US15243552

申请日：2016-08-22

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard

IPC: H01L29/747 ,  H01L29/74 ,  H01L27/02 ,  H01L29/87 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L27/0248 ,  H01L29/41716 ,  H01L29/42308 ,  H01L29/7404 ,  H01L29/7416 ,  H01L29/747 ,  H01L29/87

Abstract: A triac has a vertical structure formed from a silicon substrate having an upper surface side. A main metallization on the upper surface side has a first portion resting on a first region of a first conductivity type formed in a layer of a second conductivity type. A second portion of the main metallization rests on a portion of the layer. A gate metallization on the upper surface side rests on a second region of the first conductivity type formed in the layer in the vicinity of the first region. A porous silicon bar formed in the layer at the upper surface side has a first end in contact with the gate metallization and a second end in contact with the main metallization.

公开(公告)号：US20180108766A1

公开(公告)日：2018-04-19

申请号：US15834472

申请日：2017-12-07

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard

IPC: H01L29/747 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/747 ,  H01L29/408 ,  H01L29/66386

Abstract: A vertical power component includes a doped silicon substrate of a first conductivity type. A local well of a second conductivity type extends from an upper surface of the substrate. A passivation structure coats a peripheral region of the upper surface side of the substrate surrounding the well. This passivation structure includes, on top of and in contact with the peripheral substrate region, a first region made of a first passivation material and a second region made of a second passivation material. The second region generates, in a surface region of the substrate in contact with said second region, a local increase of the concentration of majority carriers in the substrate.