公开(公告)号：US11222957B2

公开(公告)日：2022-01-11

申请号：US16907986

申请日：2020-06-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Magali Gregoire

IPC: H01L29/45 ,  H01L21/321 ,  H01L21/285 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161

Abstract: A NiPt layer with a Pt atom concentration equal to 15% plus or minus 1% is deposited on a semiconductor region (which may, for example, be a source/drain region of a MOS transistor). An anneal is then performed at a temperature of 260° C. plus or minus 20° C., for a duration in the range from 20 to 60 seconds, in order to produce, from the Nickle-Platinum (NiPt) layer and the semiconductor material of said semiconductor region, an intermetallic layer. Advantageously, the intermetallic layer possesses a structure of heteroepitaxy with the semiconductor material, and includes free Pt atoms.

公开(公告)号：US11322363B2

公开(公告)日：2022-05-03

申请号：US16892732

申请日：2020-06-04

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Julien Borrel ,  Magali Gregoire

IPC: H01L21/3205 ,  H01L21/321 ,  H01L21/265 ,  H01L21/324 ,  H01L21/762 ,  H01L29/45

Abstract: Atoms are implanted in a semiconductor region at a higher concentration in a peripheral part of the semiconductor region than in a central part of the semiconductor region. A metallic region is then formed to cover the semiconductor region. A heat treatment is the performed to form an intermetallic region from the metallic region and the semiconductor region.

公开(公告)号：US11610813B2

公开(公告)日：2023-03-21

申请号：US17488714

申请日：2021-09-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Magali Gregoire

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: An interconnection element of an interconnection structure of an integrated circuit is manufactures by a method where a cavity is etched in an insulating layer. A silicon nitride layer is then deposited on walls and a bottom of the cavity. The nitrogen atom concentration in the silicon nitride layer increasing as a distance from an exposed surface of the silicon nitride layer increases. A copper layer is deposited on the silicon nitride layer. The cavity is further filled with copper. A heating process is performed after the deposition of the copper layer, to convert the copper layer and the silicon nitride layer to form a copper silicide layer which has a nitrogen atom concentration gradient corresponding to the gradient of the silicon nitride layer.

公开(公告)号：US11152259B2

公开(公告)日：2021-10-19

申请号：US16881689

申请日：2020-05-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Magali Gregoire

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: An interconnection element of an interconnection structure of an integrated circuit is manufactures by a method where a cavity is etched in an insulating layer. A silicon nitride layer is then deposited on walls and a bottom of the cavity. The nitrogen atom concentration in the silicon nitride layer increasing as a distance from an exposed surface of the silicon nitride layer increases. A copper layer is deposited on the silicon nitride layer. The cavity is further filled with copper. A heating process is performed after the deposition of the copper layer, to convert the copper layer and the silicon nitride layer to form a copper silicide layer which has a nitrogen atom concentration gradient corresponding to the gradient of the silicon nitride layer.