公开(公告)号：US20250015188A1

公开(公告)日：2025-01-09

申请号：US18887645

申请日：2024-09-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI ,  Romeric GAY

IPC: H01L29/78 ,  H01L21/28 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H10B41/35

Abstract: A triple-gate MOS transistor is manufactured in a semiconductor substrate including at least one active region laterally surrounded by electrically isolating regions. Trenches are etched on either side of an area of the active region configured to form a channel for the transistor. An electrically isolating layer is deposited on an internal surface of each of the trenches. Each of the trenches is then filled with a semiconductive or electrically conductive material up to an upper surface of the active region so as to form respective vertical gates on opposite sides of the channel. An electrically isolating layer is then deposited on the upper surface of the area of the active region at the channel of the transistor. At least one semiconductive or electrically conductive material then deposited on the electrically isolating layer formed at the upper surface of the active region to form a horizontal gate of the transistor.

公开(公告)号：US20210057358A1

公开(公告)日：2021-02-25

申请号：US17091466

申请日：2020-11-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre SARAFIANOS ,  Abderrezak MARZAKI

IPC: H01L23/00 ,  G06F21/87 ,  H04L9/00 ,  H01L29/06 ,  G06F21/78 ,  G06F21/55

Abstract: An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed to detect a DFA attack by fault injection into the integrated circuit.

公开(公告)号：US20190341446A1

公开(公告)日：2019-11-07

申请号：US16400286

申请日：2019-05-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI

IPC: H01L49/02 ,  H01L27/11517 ,  H01L29/06

Abstract: A capacitive element of an integrated circuit includes first and second electrodes. The first electrode is formed by a first electrically conductive layer located above a semiconductor well doped with a first conductivity type. The second electrode is formed by a second electrically conductive layer located above the first electrically conductive layer of the semiconductor well. The second electrode is further formed by a doped surface region within the semiconductor well that is heavily doped with a second conductivity type opposite the first conductivity type, wherein the doped surface region is located under the first electrically conductive layer. An inter-electrode dielectric area electrically separates the first electrode and the second electrode.

公开(公告)号：US20190237589A1

公开(公告)日：2019-08-01

申请号：US16259424

申请日：2019-01-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI

IPC: H01L29/94 ,  H01L29/66 ,  H01L27/06

CPC classification number: H01L29/945 ,  H01L27/0629 ,  H01L27/0733 ,  H01L29/66181

Abstract: A standard integrated cell includes a semiconductor region with a functional domain for logic circuits including a transistor and an adjacent continuity domain that extends out to an edge of the standard integrated cell. The edge is configured to be adjacent to another continuity domain of another standard integrated cell. The standard integrated cell further includes at capacitive element. This capacitive element may be housed in the continuity domain, for example at or near the edge. Alternatively, the capacitive element may be housed at a location which extends around a substrate region of the transistor.

公开(公告)号：US20240186236A1

公开(公告)日：2024-06-06

申请号：US18437720

申请日：2024-02-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI

IPC: H01L23/522 ,  H01L21/762 ,  H01L27/08 ,  H01L29/66

CPC classification number: H01L23/5223 ,  H01L21/76224 ,  H01L27/0805 ,  H01L29/66181

Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.

公开(公告)号：US20220375954A1

公开(公告)日：2022-11-24

申请号：US17747540

申请日：2022-05-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Romeric GAY ,  Abderrezak MARZAKI

IPC: H01L27/11526 ,  H01L27/11521

Abstract: A bipolar transistor includes a common collector region comprising a buried semiconductor layer and an annular well. A well region is surrounded by the annular well and delimited by the buried semiconductor layer. A first base region and a second base region are formed by the well region and separated from each other by a vertical gate structure. A first emitter region is implanted in the first base region, and a second emitter region is implanted in the second base region. A conductor track electrically couples the first emitter region and the second base region to configure the bipolar transistor as a Darlington-type device. Structures of the bipolar transistor may be fabricated in a co-integration with a non-volatile memory cell.

公开(公告)号：US20210151392A1

公开(公告)日：2021-05-20

申请号：US17159698

申请日：2021-01-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI ,  Pascal FORNARA

IPC: H01L23/00 ,  G04F1/00 ,  H01L21/70 ,  H01L27/01 ,  H01L27/10

Abstract: An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunnelling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.

公开(公告)号：US20210057329A1

公开(公告)日：2021-02-25

申请号：US16546569

申请日：2019-08-21

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak MARZAKI ,  Arnaud REGNIER ,  Stephan NIEL

IPC: H01L23/522 ,  H01L27/11524 ,  H01L49/02

Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

公开(公告)号：US20190043814A1

公开(公告)日：2019-02-07

申请号：US16051680

申请日：2018-08-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI ,  Christian RIVERO ,  Quentin HUBERT

IPC: H01L23/00 ,  H01L27/02 ,  G06F21/75

Abstract: An integrated electronic circuit includes a semiconductor substrate with a semiconductor well that is isolated by a buried semiconductor region located under the semiconductor well. A vertical MOS transistor formed in the semiconductor well includes a source-drain region provided by the buried semiconductor region. Backside thinning of the semiconductor substrate is detected by biasing the vertical MOS transistor into an on condition to supply a current and then comparing that current to a threshold. Current less than a threshold is indicative that the semiconductor substrate has been thinned from the backside.

公开(公告)号：US20230088967A1

公开(公告)日：2023-03-23

申请号：US17944793

申请日：2022-09-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI ,  Jean-Marc VOISIN

IPC: H01L27/02 ,  H01L23/64 ,  H01L21/768

Abstract: The integrated circuit includes a logic part including standard cells arranged in parallel rows along a first direction and in an alternation of complementary semiconductor wells. Among the standard cells, at least one capacitive filling structure belongs to two adjacent rows and includes a capacitive interface between a conductive armature and the first well, the extent of the second well in the first direction being interrupted over the length of the capacitive filling structure so that the first well occupies in the second direction the width of the two adjacent rows of the capacitive filling structure. A conductive structure electrically connects the second well on either side of the capacitive filling structure.