Driver and display device
    5.
    发明授权

    公开(公告)号:US12293695B2

    公开(公告)日:2025-05-06

    申请号:US18403346

    申请日:2024-01-03

    Abstract: A driver is disposed in a display panel, and includes a plurality of stages. At least one stage of the plurality of stages includes an input circuit which transfers an input signal to a first node in response to at least one of a clock signal and an inverted clock signal, and inverters which generate an output signal based on a voltage of the first node. At least one of the inverters includes a p-type metal-oxide-semiconductor (“PMOS”) transistor and an n-type metal-oxide-semiconductor (“NMOS”) transistor connected in series between a line transferring a relatively high gate voltage and a line transferring a relatively low gate voltage. A first active region of the PMOS transistor includes a material different from a material of a second active region of the NMOS transistor.

    Display apparatus
    6.
    发明授权

    公开(公告)号:US10727293B2

    公开(公告)日:2020-07-28

    申请号:US16235415

    申请日:2018-12-28

    Abstract: A display apparatus includes a display area in which an image is displayed and a peripheral area that is a non-display area, a base substrate, a plurality of data lines located on the base substrate in the display area and extending to the peripheral area, a plurality of detour data lines on the base substrate in the display area and in the peripheral area, and a pad portion in the peripheral area, the detour data lines and at least one of the data lines being directly connected to the pad portion, and at least one of the data lines being not directly connected to the pad portion, wherein at least one of the data lines not directly connected to the pad portion is electrically connected to the detour data line.

    Display device
    7.
    发明授权

    公开(公告)号:US10403207B2

    公开(公告)日:2019-09-03

    申请号:US15589482

    申请日:2017-05-08

    Abstract: A display device includes a plurality of pixel circuits and a gate driver including a plurality of stages configured to output a gate signal to a plurality of gate lines, respectively, to provide the gate signal to the pixel circuits. Each of the stages is divided into a plurality of sub-blocks. At least one of the pixel circuits is located between two adjacent sub-blocks of the sub-blocks.

    Gate driving circuit and display device including the same

    公开(公告)号:US09704449B2

    公开(公告)日:2017-07-11

    申请号:US14836200

    申请日:2015-08-26

    CPC classification number: G09G3/3677 G09G2300/0408 G09G2310/0281

    Abstract: The gate driving circuit includes an (m−1)-th stage externally receiving a first dummy signal for a first time period to control a turn-off, an m-th stage externally receiving a second dummy signal for the first time period to control the turn-off, an (m−2)-th stage receiving an m-th carry signal for a second time period from the m-th stage and externally receiving the second dummy signal for the second time period to control the turn-off, and an (m−3)-th stage receiving an (m−1)-th carry signal for the second time period from the (m−1)-th stage and externally receiving the first dummy signal for the first time period to control the turn-off, wherein the first time period is longer than the second time period.

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