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Patent Agency Ranking
公开(公告)号：US08980731B2
公开(公告)日：2015-03-17
申请号：US13724632
申请日：2012-12-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung Ho Kim , Sunghae Lee , Hanvit Yang , Dongwoo Kim , Chaeho Kim , Daehyun Jang , Ju-Eun Kim , Yong-Hoon Son , Sangryol Yang , Myoungbum Lee , Kihyun Hwang
IPC: H01L21/04 , H01L21/82 , H01L21/336 , H01L21/3205 , H01L29/76 , H01L29/792 , H01L27/115 , H01L29/66
CPC classification number: H01L21/04 , H01L27/11582 , H01L29/66833 , H01L29/7926
Abstract: Methods of forming a semiconductor device are provided. The methods may include forming first and second layers that are alternately and repeatedly stacked on a substrate, and forming an opening penetrating the first and second layers. The methods may also include forming a first semiconductor pattern in the opening. The methods may additionally include forming an insulation pattern on the first semiconductor pattern. The methods may further include forming a second semiconductor pattern on the insulation pattern. The methods may also include providing dopants in the first semiconductor pattern. Moreover, the methods may include thermally treating a portion of the first semiconductor pattern to form a third semiconductor pattern.
Abstract translation: 提供了形成半导体器件的方法。 所述方法可以包括形成在衬底上交替和重复堆叠的第一和第二层，以及形成穿透第一层和第二层的开口。 所述方法还可以包括在开口中形成第一半导体图案。 所述方法还可以包括在第一半导体图案上形成绝缘图案。 所述方法还可以包括在绝缘图案上形成第二半导体图案。 所述方法还可以包括在第一半导体图案中提供掺杂剂。 此外，所述方法可以包括热处理第一半导体图案的一部分以形成第三半导体图案。
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公开(公告)号：US11744077B2
公开(公告)日：2023-08-29
申请号：US17173179
申请日：2021-02-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sangmin Kang , Hanvit Yang , Jihoon Choi
Abstract: A mold including insulation layers and sacrificial layers is formed on a substrate. A channel hole is formed through the mold. A first deposition process is performed using a first precursor including silane and a second precursor including silane and a halogen element to form a first preliminary blocking layer on a sidewall of the channel hole. A second deposition process is performed using the first precursor to form a second preliminary blocking layer on the sidewall of the channel hole. The first and second preliminary blocking layers form a third preliminary blocking layer. An oxidation process is performed on the third preliminary blocking layer to transform the third preliminary blocking into a first blocking layer. A charge storage layer, a tunnel insulation layer, and a channel layer are formed on the first blocking layer. The sacrificial layer is replaced with a gate electrode.
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公开(公告)号：US12213316B2
公开(公告)日：2025-01-28
申请号：US17720376
申请日：2022-04-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Suhwan Lim , Nambin Kim , Samki Kim , Taehun Kim , Hanvit Yang , Changhee Lee , Jaehun Jung , Hyeongwon Choi
Abstract: A semiconductor device includes a lower structure including a semiconductor substrate and circuit devices on the semiconductor substrate; a stack structure including interlayer insulating layers and gate electrodes alternating in a vertical direction; and a channel structure penetrating the stack structure. The channel structure includes a core insulating layer, a channel layer, a gate dielectric layer, and a channel pad. A portion of the channel pad overlaps an uppermost gate electrode among the gate electrodes in a horizontal direction. The channel pad includes a first pad layer and a second pad layer on the first pad layer. The second pad layer includes doped polysilicon that is doped with impurities and having N-type conductivity. The first pad layer includes at least one of an undoped polysilicon region and a doped polysilicon region having N-type conductivity and having an impurity concentration lower than an impurity concentration of the second pad layer.
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公开(公告)号：US11594548B2
公开(公告)日：2023-02-28
申请号：US17029269
申请日：2020-09-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sangmin Kang , Hanvit Yang
IPC: H01L27/11575 , H01L23/48 , H01L23/528 , H01L27/11582 , H01L21/768 , H01L27/11573 , H01L23/50
Abstract: A semiconductor device includes a substrate, a lower structure on the substrate, the lower structure including a first wiring structure, a second wiring structure, and a lower insulating structure covering the first and second wiring structures, a first pattern layer including a plate portion and a via portion, the plate portion being on the lower insulating structure and the via portion extending into the lower insulating structure from a lower portion of the plate portion and overlapping the first wiring structure, a graphene-like carbon material layer in contact with the via portion and the first wiring structure between the via portion and the first wiring structure, gate layers stacked in a vertical direction perpendicular to an upper surface of the substrate and spaced apart from each other on the first pattern layer, and a memory vertical structure penetrating through the gate layers in the vertical direction.
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公开(公告)号：US20210384200A1
公开(公告)日：2021-12-09
申请号：US17173179
申请日：2021-02-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sangmin Kang , Hanvit Yang , Jihoon Choi
IPC: H01L27/1157 , H01L27/11582
Abstract: A mold including insulation layers and sacrificial layers is formed on a substrate. A channel hole is formed through the mold. A first deposition process is performed using a first precursor including silane and a second precursor including silane and a halogen element to form a first preliminary blocking layer on a sidewall of the channel hole. A second deposition process is performed using the first precursor to form a second preliminary blocking layer on the sidewall of the channel hole. The first and second preliminary blocking layers form a third preliminary blocking layer. An oxidation process is performed on the third preliminary blocking layer to transform the third preliminary blocking into a first blocking layer. A charge storage layer, a tunnel insulation layer, and a channel layer are formed on the first blocking layer. The sacrificial layer is replaced with a gate electrode.
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