公开(公告)号：US11848285B2

公开(公告)日：2023-12-19

申请号：US17671818

申请日：2022-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangwuk Park ,  Youngmin Lee ,  Inyoung Lee ,  Sungdong Cho

IPC: H01L23/58 ,  H01L25/065 ,  H01L23/522

CPC classification number: H01L23/585 ,  H01L23/5226 ,  H01L25/0657

Abstract: A semiconductor chip, a semiconductor package including the same, and a method of fabricating the same, the semiconductor chip including a substrate that includes a device region and an edge region; a device layer and a wiring layer that are sequentially stacked on the substrate; a subsidiary pattern on the wiring layer on the edge region; a first capping layer that covers a sidewall of the subsidiary pattern, a top surface of the wiring layer, and a sidewall of the wiring layer, the first capping layer including an upper outer sidewall and a lower outer sidewall, the lower outer sidewall being offset from the upper outer sidewall; and a buried dielectric pattern in contact with the lower outer sidewall of the first capping layer and spaced apart from the upper outer sidewall of the first capping layer.

公开(公告)号：US11784168B2

公开(公告)日：2023-10-10

申请号：US17748164

申请日：2022-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongwon Choi ,  Wonkeun Kim ,  Inyoung Lee

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/06 ,  H01L25/50 ,  H01L2224/06517 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A semiconductor chip including a semiconductor substrate having a first surface and a second surface and having an active layer in a region adjacent to the first surface, a first through electrode penetrating at least a portion of the semiconductor substrate and connected to the active layer, a second through electrode located at a greater radial location from the center of the semiconductor substrate than the first through electrode, penetrating at least a portion of the semiconductor substrate, and connected to the active layer. The semiconductor chip also including a first chip connection pad having a first height and a first width, located on the second surface of the semiconductor substrate, and connected to the first through electrode, and a second chip connection pad having a second height greater than the first height and a second width greater than the first width, located on the second surface of the semiconductor substrate, and connected to the second through electrode.

公开(公告)号：US11705379B2

公开(公告)日：2023-07-18

申请号：US17087879

申请日：2020-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Lee ,  Won Kim ,  Haeseok Park ,  Ilgeun Jung ,  Jinkuk Bae ,  Inyoung Lee ,  Sungdong Cho

IPC: H01L23/31 ,  H01L25/065 ,  H01L25/18 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L23/3171 ,  H01L23/3135 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L22/12 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/13016 ,  H01L2224/1357 ,  H01L2224/13147 ,  H01L2224/13564 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/14515 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/1436

Abstract: A semiconductor package may include a base, a first chip on the base, and first connection patterns that connect and couple the base and the first chip. The first chip may include a substrate, pad patterns on the substrate, a passivation layer on the substrate and having openings, and pillars on the substrate, the pad patterns include a first signal pad and a second signal pad, the first connection patterns are in contact with the pillars, the pillars include a first signal pillar in contact with the first signal pad and a second signal pillar in contact with the second signal pad, the openings in the passivation layer include a first opening having a sidewall facing a side surface of the first signal pillar and surrounding the side surface of the first signal pillar, and a second opening having a sidewall facing a side surface of the second signal pillar and surrounding the side surface of the second signal pillar, and a maximum width of the second opening is greater than a maximum width of the first opening.

公开(公告)号：US20180123224A1

公开(公告)日：2018-05-03

申请号：US15845703

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo JUNG ,  Taeyoung Kim ,  Inyoung Lee ,  Wonseok Jeong ,  Jae-Bong Chun

IPC: H01Q1/27 ,  H01Q1/48 ,  H04B5/00 ,  H04W4/00 ,  H01Q1/38

CPC classification number: H01Q1/273 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q9/42 ,  H04B5/0031 ,  H04W4/80

Abstract: A device is provided. The device includes a housing forming at least one portion of a surface of the device, wherein the at least one portion of the surface includes first and second surfaces facing opposite to each other; a display at least partially housed in the housing and including a display area visible via at least one portion of the first surface; a substantially circular radiating element at least partially forming the first surface; a ground element between the first and second surfaces; a conductive element below the ground element; wireless communication circuitry electrically connected with the radiating element and establishing communication with an external electronic device; and a processor electrically connecting the conductive element with the ground element if a radiation characteristic relative to the radiating element satisfies a condition; and disconnecting the conductive element with the ground element if the radiation characteristic does not satisfy the condition.

公开(公告)号：US09859612B2

公开(公告)日：2018-01-02

申请号：US15234708

申请日：2016-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Jung ,  Taeyoung Kim ,  Inyoung Lee ,  Wonseok Jeong ,  Jae-Bong Chun

IPC: H01Q1/12 ,  H01Q1/27 ,  H01Q1/48 ,  H04B5/00 ,  H04W4/00 ,  H01Q1/38

CPC classification number: H01Q1/273 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q9/42 ,  H04B5/0031 ,  H04W4/80

Abstract: An electronic device and a method of operating an electronic device are provided. The electronic device includes a housing including a first face and a second face that faces in a direction opposite to the first face; a display exposed through the first face of the housing; a ground member disposed between the first face and the second face; an antenna radiator at least partially disposed within the housing and/or on a portion of the housing; a communication circuit electrically connected to the antenna radiator; a conductive member disposed within the housing or forming a portion of the second face of the housing; and a control circuit electrically connected to the ground member and the conductive member, wherein the control circuit is configured to selectively connect the conductive member to the ground member if the antenna radiator and the communication circuit are electrically connected to each other.

公开(公告)号：US11923292B2

公开(公告)日：2024-03-05

申请号：US17307212

申请日：2021-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinkuk Bae ,  Hyunsoo Chung ,  Inyoung Lee ,  Donghyeon Jang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5226 ,  H01L21/76873 ,  H01L23/3128 ,  H01L24/09 ,  H01L24/17

Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad disposed on the semiconductor substrate, and a pillar pattern disposed on the conductive pad. The semiconductor device further includes a solder seed pattern disposed on the pillar pattern, and a solder portion disposed on the pillar pattern and the solder seed pattern. A first width of the solder seed pattern is less than a second width of a top surface of the pillar pattern.

公开(公告)号：US11824260B2

公开(公告)日：2023-11-21

申请号：US16972111

申请日：2019-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sewoong Kim ,  Chaeup Yoo ,  Sumin Yun ,  Woosuk Kang ,  Inyoung Lee

IPC: H01Q1/38 ,  H01Q1/24 ,  H05K1/02 ,  H05K5/00 ,  H05K7/14

CPC classification number: H01Q1/38 ,  H01Q1/24 ,  H05K1/02 ,  H05K1/0243 ,  H05K5/00 ,  H05K5/0017 ,  H05K5/0086 ,  H05K7/14 ,  H05K7/1427 ,  H05K2201/10037

Abstract: According to an embodiment, an electronic device may include a display including a first conductive plate, a printed circuit board interposed between a rear surface of housing and the display and including a second conductive plate, a first conductive pattern and a second conductive pattern that are interposed between the display and the printed circuit board, a wireless communication circuit electrically connected to the first conductive pattern and transmitting or receiving an RF signal of a first frequency or an RF signal of a second frequency, and at least one processor electrically connected to the wireless communication circuit. Besides, various embodiments as understood from the specification are also possible.

公开(公告)号：US11587897B2

公开(公告)日：2023-02-21

申请号：US17143224

申请日：2021-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongwon Shin ,  Yeonjin Lee ,  Inyoung Lee ,  Jimin Choi ,  Jung-Hoon Han

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/00

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a conductive pad on a first surface of the semiconductor substrate, a passivation layer on the first surface of the semiconductor substrate, the passivation layer having a first opening that exposes the conductive pad, an organic dielectric layer on the passivation layer, the organic dielectric layer having a second opening, and a bump structure on the conductive pad and in the first and second openings. The organic dielectric layer includes a material different from a material of the passivation layer. The second opening is spatially connected to the first opening and exposes a portion of the passivation layer. The bump structure includes a pillar pattern in contact with the passivation layer and the organic dielectric layer.

公开(公告)号：US20210384162A1

公开(公告)日：2021-12-09

申请号：US17172478

申请日：2021-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongwon Choi ,  Wonkeun Kim ,  Inyoung Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor chip including a semiconductor substrate having a first surface and a second surface and having an active layer in a region adjacent to the first surface, a first through electrode penetrating at least a portion of the semiconductor substrate and connected to the active layer, a second through electrode located at a greater radial location from the center of the semiconductor substrate than the first through electrode, penetrating at least a portion of the semiconductor substrate, and connected to the active layer. The semiconductor chip also including a first chip connection pad having a first height and a first width, located on the second surface of the semiconductor substrate, and connected to the first through electrode, and a second chip connection pad having a second height greater than the first height and a second width greater than the first width, located on the second surface of the semiconductor substrate, and connected to the second through electrode.

公开(公告)号：US11342310B2

公开(公告)日：2022-05-24

申请号：US17172478

申请日：2021-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongwon Choi ,  Wonkeun Kim ,  Inyoung Lee

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor chip including a semiconductor substrate having a first surface and a second surface and having an active layer in a region adjacent to the first surface, a first through electrode penetrating at least a portion of the semiconductor substrate and connected to the active layer, a second through electrode located at a greater radial location from the center of the semiconductor substrate than the first through electrode, penetrating at least a portion of the semiconductor substrate, and connected to the active layer. The semiconductor chip also including a first chip connection pad having a first height and a first width, located on the second surface of the semiconductor substrate, and connected to the first through electrode, and a second chip connection pad having a second height greater than the first height and a second width greater than the first width, located on the second surface of the semiconductor substrate, and connected to the second through electrode.