公开(公告)号：US12302570B2

公开(公告)日：2025-05-13

申请号：US17739845

申请日：2022-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji Kanamori ,  Seungyoon Kim ,  Jeehoon Han

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a stack structure of alternating interlayer insulating layers and gate electrodes, a separation structure vertically penetrating the stack structure and extending in a first direction, to separate the gate electrodes in a second direction, and vertical structures vertically penetrating the stack structure and arranged at a constant pitch. The vertical structures are arranged along array lines sequentially arranged in the second direction away from a side of the separation structure in a plan view. The vertical structures include a channel structure including a channel layer, a contact structure including a metal plug having an upper surface on a level higher than that of an upper surface of the channel structure, and a dummy structure disposed adjacent to the contact structure. The channel structure, the dummy structure, and the contact structure are disposed to be aligned with each other on at least one of the array lines.

公开(公告)号：US11521981B2

公开(公告)日：2022-12-06

申请号：US17095821

申请日：2020-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangyoung Jung ,  Sangyoun Jo ,  Kohji Kanamori ,  Jeehoon Han

IPC: H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  G11C7/18 ,  H01L27/11519 ,  G11C16/08 ,  H01L27/11534 ,  H01L27/11565

Abstract: A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.

公开(公告)号：US11450681B2

公开(公告)日：2022-09-20

申请号：US16844234

申请日：2020-04-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haemin Lee ,  Jongwon Kim ,  Shinhwan Kang ,  Kohji Kanamori ,  Jeehoon Han

IPC: H01L27/1157 ,  H01L27/11556 ,  H01L27/11521 ,  H01L27/11578

Abstract: A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate.

公开(公告)号：US10998301B2

公开(公告)日：2021-05-04

申请号：US16531778

申请日：2019-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji Kanamori ,  Hyun Mog Park ,  Yong Seok Kim ,  Kyung Hwan Lee ,  Jun Hee Lim ,  Jee Hoon Han

IPC: H01L25/18 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor device includes a first semiconductor structure including circuit devices and first bonding pads; and a second semiconductor structure connected to the first semiconductor structure, the second semiconductor structure including a base layer; a first memory cell structure including first gate electrodes and first channels penetrating through the first gate electrodes; a second memory cell structure including second gate electrodes and second channels penetrating through the second gate electrodes; bit lines between the first and the second memory cell structures, and electrically connected to the first and second channels in common; first and second conductive layers on the second surface of the base layer; a pad insulating layer having an opening exposing a portion of the second conductive layer; and second bonding pads disposed to correspond to the first bonding pads in a lower portion of the second memory cell structure.

公开(公告)号：US10861874B2

公开(公告)日：2020-12-08

申请号：US16445433

申请日：2019-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Hwan Lee ,  Yong-Seok Kim ,  Jun-Hee Lim ,  Kohji Kanamori

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/311 ,  H01L21/768 ,  H01L21/762

Abstract: A vertical semiconductor device includes conductive pattern structures extending in a first direction, a trench between two adjacent conductive pattern structures in a second direction crossing the first direction, a memory layer disposed on sidewalls of the trench, first insulation layers disposed in the trench and spaced apart from each other in the first direction, channel patterns disposed on the memory layer and in the trench and spaced apart from each other in the first direction, and etch stop layer patterns disposed in the trench. Each conductive pattern structure includes conductive patterns and insulation layers alternately stacked on an upper surface of the substrate. Each etch stop layer pattern is disposed between a corresponding first insulation layer and the blocking dielectric layer. Etch stop layer patterns are spaced apart from each other in the first direction.

公开(公告)号：US20200381448A1

公开(公告)日：2020-12-03

申请号：US16710198

申请日：2019-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Kohji Kanamori ,  Minhan Shin

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573

Abstract: Three-dimensional semiconductor memory devices are provided. A three-dimensional semiconductor memory device includes a stack structure that includes gate electrodes on a substrate. The three-dimensional semiconductor memory device includes a first vertical structure, a second vertical structure, a third vertical structure, and a fourth vertical structure that penetrate the stack structure and are sequentially arranged in a zigzag shape along a first direction. Moreover, the three-dimensional semiconductor memory device includes a first bit line that extends in the first direction. The first bit line vertically overlaps the second vertical structure and the fourth vertical structure. Centers of the second and fourth vertical structures are spaced apart at the same distance from the first bit line. The first vertical structure is spaced apart at a first distance from the first bit line. The third vertical structure is spaced apart at a second distance from the first bit line.

公开(公告)号：US10854630B2

公开(公告)日：2020-12-01

申请号：US16526139

申请日：2019-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-soo Kim ,  Yong-seok Kim ,  Tae-hun Kim ,  Min-kyung Bae ,  Jae-hoon Jang ,  Kohji Kanamori

IPC: H01L27/11582 ,  H01L29/08 ,  H01L29/78 ,  H01L27/11565

Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, a common source extension structure including a first semiconductor layer having an n-type conductivity and a gate insulating layer between the substrate and the channel structures, a plurality of gate electrodes on the common source extension structure and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension structure and including a second semiconductor layer having an n-type conductivity. An upper portion of the common source extension structure has a first width, and a lower portion of the common source extension structure has a second width smaller than the first width.

公开(公告)号：US20200144288A1

公开(公告)日：2020-05-07

申请号：US16730276

申请日：2019-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji Kanamori ,  Young-Hwan Son ,  Byung-Kwan You ,  Eun-Taek Jung

IPC: H01L27/11582 ,  H01L21/28 ,  H01L49/02 ,  H01L27/1157 ,  H01L29/66 ,  H01L21/56 ,  H01L21/764 ,  H01L21/768 ,  H01L23/532 ,  H01L29/423

Abstract: A vertical memory device includes first, second and third impurity regions sequentially stacked in a first direction substantially perpendicular to an upper surface of a substrate, a gate electrode structure including gate electrodes spaced apart from each other in the first direction on the third impurity region, a channel extending through the gate electrode structure, the second and third impurity regions, and an upper portion of the first impurity region on the substrate in the first direction, and a charge storage structure covering a portion of an outer sidewall and a lower surface of the channel. The channel directly contacts a sidewall of the second impurity region.

公开(公告)号：US20200091189A1

公开(公告)日：2020-03-19

申请号：US16692385

申请日：2019-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Kim ,  Shin Hwan Kang ,  Jae Hoon Jang ,  Kohji Kanamori

IPC: H01L27/11582

Abstract: A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.

公开(公告)号：US20190326316A1

公开(公告)日：2019-10-24

申请号：US16209323

申请日：2018-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG-HWAN SON ,  Kohji Kanamori ,  Shin-Hwan Kang ,  Young Jin Kwon

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/535

Abstract: A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.