公开(公告)号：US10707164B2

公开(公告)日：2020-07-07

申请号：US16296388

申请日：2019-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangho Rha ,  Jongmin Baek ,  Wookyung You ,  Sanghoon Ahn ,  Nae-In Lee

IPC: H01L23/528 ,  H01L21/306 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/288 ,  H01L21/321

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

公开(公告)号：US10446774B2

公开(公告)日：2019-10-15

申请号：US15870922

申请日：2018-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi-Koan Hong ,  Kwang-Jin Moon ,  Nae-In Lee ,  Ho-Jin Lee

IPC: H01L23/48 ,  H01L51/44 ,  H01L25/065 ,  H01L23/532 ,  H01L23/538 ,  H01L21/768 ,  H01L51/00 ,  H01L23/00 ,  B82Y99/00 ,  B82Y10/00

Abstract: A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

公开(公告)号：US20190189744A1

公开(公告)日：2019-06-20

申请号：US16274350

申请日：2019-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Nam Kim ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Jong-Jin Lee ,  Ho-Yun Jeon ,  Eun-Ji Jung

IPC: H01L29/08 ,  H01L23/532 ,  H01L27/12 ,  H01L27/088 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L29/0847 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/0886 ,  H01L27/1211

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

公开(公告)号：US10217820B2

公开(公告)日：2019-02-26

申请号：US15632884

申请日：2017-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Nam Kim ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Jong-Jin Lee ,  Ho-Yun Jeon ,  Eun-Ji Jung

IPC: H01L29/08 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L27/12

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

公开(公告)号：US09281277B2

公开(公告)日：2016-03-08

申请号：US14527842

申请日：2014-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min Baek ,  Sang-Ho Rha ,  Woo-Kyung You ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Ki-Chul Kim ,  Jeon-Il Lee

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wiring structure includes a first insulation layer, a plurality of wiring patterns, a protection layer pattern and a second insulation layer. The first insulation layer may be formed on a substrate. A plurality of wiring patterns may be formed on the first insulation layer, and each of the wiring patterns may include a metal layer pattern and a barrier layer pattern covering a sidewall and a bottom surface of the metal layer pattern. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen.

Abstract translation: 布线结构包括第一绝缘层，多个布线图案，保护层图案和第二绝缘层。 第一绝缘层可以形成在基板上。 可以在第一绝缘层上形成多个布线图案，并且每个布线图案可以包括覆盖金属层图案的侧壁和底表面的金属层图案和阻挡层图案。 保护层图案可以覆盖每个布线图案的顶表面，并且包括相对于氧具有高反应性的材料。 保护层图案可以覆盖每个布线图案的顶表面，并且包括相对于氧具有高反应性的材料。

公开(公告)号：US20150194333A1

公开(公告)日：2015-07-09

申请号：US14516774

申请日：2014-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo-Kyung You ,  Sang-Ho Rha ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee

IPC: H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/3065 ,  H01L21/764 ,  H01L21/76826 ,  H01L21/76849 ,  H01L21/76877

Abstract: Methods of forming a wiring structure are provided including forming an insulating interlayer on a substrate and forming a sacrificial layer on the insulating interlayer. The sacrificial layer is partially removed to define a plurality of openings. Wiring patterns are formed in the openings. The sacrificial layer is transformed into a modified sacrificial layer by a plasma treatment. The modified sacrificial layer is removed by a wet etching process. An insulation layer covering the wiring patterns is formed on the insulating interlayer. The insulation layer defines an air gap therein between neighboring wiring patterns.

Abstract translation: 提供形成布线结构的方法包括在基板上形成绝缘中间层并在绝缘中间层上形成牺牲层。 牺牲层被部分地去除以限定多个开口。 在开口中形成接线图案。 通过等离子体处理将牺牲层转变成改性的牺牲层。 通过湿蚀刻工艺去除改性牺牲层。 在绝缘中间层上形成覆盖布线图案的绝缘层。 绝缘层在相邻布线图案之间限定了气隙。

公开(公告)号：US10700164B2

公开(公告)日：2020-06-30

申请号：US16274350

申请日：2019-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Nam Kim ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Jong-Jin Lee ,  Ho-Yun Jeon ,  Eun-Ji Jung

IPC: H01L29/08 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L27/12

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

公开(公告)号：US20170294337A1

公开(公告)日：2017-10-12

申请号：US15632884

申请日：2017-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Nam KIM ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Jong-Jin Lee ,  Ho-Yun Jeon ,  Eun-Ji Jung

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L29/0847 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/0886 ,  H01L27/1211

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

公开(公告)号：US09768300B2

公开(公告)日：2017-09-19

申请号：US15406018

申请日：2017-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

公开(公告)号：US09558994B2

公开(公告)日：2017-01-31

申请号：US15205168

申请日：2016-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wookyung You ,  Sanghoon Ahn ,  Sangho Rha ,  Jongmin Baek ,  Nae-In Lee

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate including a first region and a second region, first conductive patterns disposed on the first region and spaced apart from each other by a first distance, second conductive patterns disposed on the second region and spaced apart from each other by a second distance greater than the first distance, and an interlayer insulating layer disposed between the second conductive patterns and including at least one recess region having a width corresponding to the first distance.

Abstract translation: 一种半导体器件包括：包括第一区域和第二区域的衬底;第一导电图案，设置在第一区域上并且彼此间隔开第一距离;第二导电图案，设置在第二区域上并且彼此间隔开 第二距离大于第一距离，以及层间绝缘层，设置在第二导电图案之间并且包括具有对应于第一距离的宽度的至少一个凹部区域。