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公开(公告)号：US11336304B2
公开(公告)日：2022-05-17
申请号：US16908593
申请日：2020-06-22
Applicant: Seagate Technology LLC
Inventor： Deepak Sridhara , Jason Bellorado , Ara Patapoutian , Marcus Marrow
Abstract: In one implementation, the disclosure provides a decoding system that concurrently executes a read sample combining recovery process and an iterative outer code (IOC) recovery process. Performing the read sample combining recovery process entails executing multiple rounds of logic that each provide for combining together different data samples read from a data block. The IOC recovery process is performed at least partially concurrent with the read sample combining recovery process and each round of the IOC recovery process is based on newly-updated data samples generated by the read sample combining recovery process.
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公开(公告)号：US11797396B2
公开(公告)日：2023-10-24
申请号：US16944039
申请日：2020-07-30
Applicant: Seagate Technology LLC
Inventor： Deepak Sridhara , Jason Bellorado , Ara Patapoutian , Marcus Marrow
CPC classification number: G06F11/1471 , G06F3/064 , G06F3/0619 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G06F11/0772
Abstract: An error recovery process provides for selecting a first recovery scheme for a decoding attempt on a first subset of a set of failed data blocks read from a data track; selecting a second different recovery scheme for a decoding attempt on a second subset of the set of failed data blocks read from the data track; and during a single revolution of the data track, performing operations to decode a first subset of the failed data blocks according to the first recovery scheme operations to decode the second subset of the failed data blocks according to the second different recovery scheme.
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公开(公告)号：US11042439B1
公开(公告)日：2021-06-22
申请号：US15345440
申请日：2016-11-07
Applicant: Seagate Technology LLC
Inventor： Deepak Sridhara , Ara Patapoutian , Prafulla B Reddy
Abstract: An apparatus may include a circuit configured to initialize a read operation to read one or more requested data segments of a respective data unit having a plurality of data segments. Based on a number of failed data segments of the requested data segments and an erasure capability of an outer code error correction scheme, the circuit may perform erasure recovery to recover the failed data segments. Based on the number of failed data segments, the erasure capability of the outer code error correction scheme, and a threshold value, the circuit may perform iterative outer code recovery to recover the failed data segments.
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公开(公告)号：US10140180B1
公开(公告)日：2018-11-27
申请号：US15344423
申请日：2016-11-04
Applicant: Seagate Technology LLC
Inventor： Deepak Sridhara , Ara Patapoutian , Prafulla B Reddy
Abstract: Systems and methods are disclosed for performing segment-based outer code recovery at a data storage device. An apparatus may comprise a circuit configured to disable outer code error recovery, and perform a read operation spanning a plurality of segments of a data storage medium, a segment including a plurality of sectors. The circuit may identify one or more segments from the plurality of segments that have one or more sectors with an error. For an identified segment of the one or more segments, the circuit may perform a re-read operation with outer code error recovery enabled, and perform outer code recovery on sectors with an error within the identified segment.
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公开(公告)号：US08885277B1
公开(公告)日：2014-11-11
申请号：US14143856
申请日：2013-12-30
Applicant: Seagate Technology LLC
Inventor： Fatih Erden , Barmeshwar Vikramaditya , Deepak Sridhara , William Radich
IPC: G11B5/09
CPC classification number: G11B5/4886 , G11B5/012 , G11B20/1403 , G11B20/1833 , G11B2005/0005
Abstract: Technologies are described herein for implementing modulation coding schemes for TDMR. A data sequence is received to be stored on a first data track of a recording media. The first data sequence is encoded into a first codeword sequence using a modulation coding scheme, and the first codeword sequence is written to the first data track of the recording media. Subsequently, a second data sequence is received to be stored on a second data track of the recording media, the second data track being adjacent to the first data track. A second codeword sequence is generated for the second data sequence based on the first codeword sequence on the first data track, and the second codeword sequence is written to the second data track of the recording media.
Abstract translation: 这里描述了用于实现TDMR的调制编码方案的技术。 接收数据序列以存储在记录介质的第一数据轨道上。 使用调制编码方案将第一数据序列编码成第一码字序列，并将第一码字序列写入记录介质的第一数据轨道。 随后，接收第二数据序列以存储在记录介质的第二数据轨道上，第二数据轨道与第一数据轨道相邻。 基于第一数据磁道上的第一码字序列为第二数据序列生成第二码字序列，并且将第二码字序列写入记录介质的第二数据轨道。
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Patent Agency Ranking
公开(公告)号：US11757472B1
公开(公告)日：2023-09-12
申请号：US17744874
申请日：2022-05-16
Applicant: Seagate Technology LLC
Inventor： Ara Patapoutian , Jason Charles Jury , Deepak Sridhara , Jason Bellorado
CPC classification number: H03M13/2778 , G06F7/78 , H03M13/05
Abstract: A method includes encoding a sector of data to be written to a data storage device with a single error correcting code (ECC). The sector of data is divided into N individually readable and writeable portions, with N≥2. The individually readable and writeable portions of the sector of data are separated with a space between the portions of the sector of data in a pattern.
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公开(公告)号：US11233528B1
公开(公告)日：2022-01-25
申请号：US17022549
申请日：2020-09-16
Applicant: Seagate Technology LLC
Inventor： Ivana Djurdjevic , Ara Patapoutian , Deepak Sridhara , Bengt Anders Ulriksson , Jeffrey John Pream
IPC: H03M13/11
Abstract: A low-density parity check (LDPC) decoder includes a variable node unit (VNU) comprising a plurality of variable nodes configured to perform sums. A first message mapper of the LDPC decoder receives first n1-bit indices from likelihood ratio (LLR) input and maps the first n1-bit indices to first numerical values that are input to the variable nodes of the VNU. A second message mapper of the LDPC decoder receives second n2-bit indices from a check node unit (CNU) and maps the second n2-bit indices to second numerical values that are input to the variable nodes of the VNU. The CNU includes a plurality of check nodes that perform parity check operations. The first and second numerical values having ranges that are larger than what can be represented in n1-bit and n2-bit binary, respectively.
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公开(公告)号：US11121729B1
公开(公告)日：2021-09-14
申请号：US16944050
申请日：2020-07-30
Applicant: Seagate Technology LLC
Inventor： Deepak Sridhara , Jason Bellorado , Ara Patapoutian , Marcus Marrow
Abstract: An error recovery process provides for identifying a set of failed data blocks read from a storage medium during execution of a read command, populating sample buffers in a read channel with data of a first subset of the set of failed data blocks, and initiating an error recovery process on the data in the sample buffers. Responsive to successful recovery of one or more data blocks in the first subset, recovered data is released from the sample buffers and sample buffers locations previously-storing the recovered data are repopulated with data of a second subset of the set of failed data blocks. The error recovery process is then initiated on the data of the second subset of the failed data blocks while the error recovery process is ongoing with respect to data of the first subset of failed data blocks remaining in the sample buffers.
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公开(公告)号：US10804932B2
公开(公告)日：2020-10-13
申请号：US16233555
申请日：2018-12-27
Applicant: Seagate Technology LLC
Inventor： Deepak Sridhara , Rishi Ahuja , William M. Radich , Ara Patapoutian
Abstract: In one implementation, the disclosure provides a system including a detector configured to generate an output of a first log-likelihood ratio for each bit in an input data stream. The system also includes at least one look-up table providing a mapping of the first log-likelihood ratio to a second log-likelihood ratio. The mapping between the first log-likelihood ratio and the second log-likelihood ratio is non-linear. The system also includes a decoder configured to generate an output data stream using the second log-likelihood ratio to generate a value for each bit in the input data stream.
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公开(公告)号：US20200212934A1
公开(公告)日：2020-07-02
申请号：US16245080
申请日：2019-01-10
Applicant: Seagate Technology LLC
Inventor： Deepak Sridhara , Rishi Ahuja , William M. Radich , Ara Patapoutian
Abstract: In one implementation, the disclosure provides a system including a detector configured to generate an output of a first log-likelihood ratio for each bit in an input data stream. The system also includes at least one look-up table providing a mapping of the first log-likelihood ratio to a second log-likelihood ratio. The mapping between the first log-likelihood ratio and the second log-likelihood ratio is non-linear. The system also includes a decoder configured to generate an output data stream using the second log-likelihood ratio to generate a value for each bit in the input data stream.
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