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    Phase locking multiple clocks of different frequencies
    1.
    发明授权
    Phase locking multiple clocks of different frequencies 有权

    公开(公告)号：US11735220B2

    公开(公告)日：2023-08-22

    申请号：US17562426

    申请日：2021-12-27

    Applicant: Seagate Technology LLC

    Inventor： Zheng Wu ,  Jason Bellorado

    IPC: G11B20/10 ,  G11B5/596 ,  G11B11/105

    CPC classification number: G11B11/10578 ,  G11B5/59655

    Abstract: Systems and methods are disclosed for phase locking of a clock. In some embodiments, a phase locked clock (PLC) module can phase-lock a write clock to a media written with multiple servo zones of different frequencies. In some implementations, this can be utilized to perform a self-servo write (SSW) of a disc surface within a hard disc drive (HDD). A PLC module can perform a method of writing with a single frequency phase coherently while a read element passes over servo zones with different frequencies. While the PLC module can perform such methods for a SSW process, the methods can also be utilized for other applications that can benefit from writing with a single frequency phase coherently based on servo zones with different frequencies.

    Estimating read offset in a drive using machine learning
    2.
    发明授权
    Estimating read offset in a drive using machine learning 有权

    公开(公告)号：US11646059B2

    公开(公告)日：2023-05-09

    申请号：US17460735

    申请日：2021-08-30

    Applicant: Seagate Technology LLC

    Inventor： Zheng Wang ,  Ara Patapoutian ,  Jason Bellorado ,  William M. Radich

    IPC: G11B21/10 ,  G06N3/04

    CPC classification number: G11B21/106 ,  G06N3/04

    Abstract: Components are extracted from user data being read from a reader of a hard disk drive. The components collectively indicate both a magnitude and direction of a read offset of the reader over a track. The components are input to a machine-learning processor during operation of the hard disk drive, causing the machine-learning processor to produce an output. A read offset of the reader is estimated during the operation of the hard drive head based on the output of the machine learning processor. While reading the user data, a radial position of the reader over the track is adjusted via an actuator based on the estimated read offset.

    MAGNETORESISTIVE ASYMMETRY COMPENSATION
    4.
    发明申请
    MAGNETORESISTIVE ASYMMETRY COMPENSATION 有权

    公开(公告)号：US20220247418A1

    公开(公告)日：2022-08-04

    申请号：US17582376

    申请日：2022-01-24

    Applicant: Seagate Technology LLC

    Inventor： Jason Bellorado ,  Marcus Marrow ,  Zheng Wu

    IPC: H03M1/06 ,  H03G3/30 ,  G11B5/027 ,  G11B20/10 ,  G11B5/012

    Abstract: Systems and methods are disclosed for magnetoresistive asymmetry (MRA) compensation using a digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing analog offset compensation to constrain an extremum of the analog signal to adjust a dynamic range based on an input range of an analog-to-digital converter (ADC), rather than to modify the analog signal to have a zero mean. The method may further comprise converting the analog signal to a digital sample sequence via the ADC; performing, via a digital MRA compensation circuit, digital MRA compensation on the digital sample sequence; receiving, via a digital backend (DBE) subsystem, the digital sample sequence prior to digital MRA compensation; and generating, via a DBE, a bit sequence corresponding to the analog signal based on an output of the DBE subsystem and an output of the digital MRA compensation circuit.

    Dynamic timing recovery bandwidth modulation for phase offset mitigation
    6.
    发明授权
    Dynamic timing recovery bandwidth modulation for phase offset mitigation 有权

    公开(公告)号：US11018842B1

    公开(公告)日：2021-05-25

    申请号：US16051252

    申请日：2018-07-31

    Applicant: Seagate Technology LLC

    Inventor： Jason Bellorado ,  Marcus Marrow ,  Zheng Wu

    IPC: H04L7/00 ,  H03L7/08

    Abstract: An apparatus may include a sampling circuit configured to produce a sequence of input samples based on a continuous time input signal and a sample clock signal, the sampling phase of the sequence of input samples based on a phase control value output by a timing recovery circuit. In addition, the apparatus may include the timing recovery circuit configured to receive the sequence of input samples, detect, for a current sample of the sequence of input samples, a phase offset in the sampling phase of the sequence of input samples, the phase offset being a deviation of the sampling phase from an expected phase, and in response to detecting the phase offset, select a bandwidth for timing recovery. Further, the timing recovery circuit may generate an updated phase control value based on the selected bandwidth for timing recovery.

    MULTI-SIGNAL REALIGNMENT FOR CHANGING SAMPLING CLOCK
    9.
    发明申请
    MULTI-SIGNAL REALIGNMENT FOR CHANGING SAMPLING CLOCK 审中-公开

    公开(公告)号：US20200005819A1

    公开(公告)日：2020-01-02

    申请号：US16570785

    申请日：2019-09-13

    Applicant: Seagate Technology LLC

    Inventor： Jason Bellorado ,  Marcus Marrow ,  Zheng Wu

    IPC: G11B5/596 ,  H03L7/091 ,  H03M1/00 ,  G11B20/10 ,  H03L7/081 ,  H03L7/07 ,  H03K5/131 ,  H03K5/135 ,  H03M13/41

    Abstract: An apparatus may include a circuit configured to receive first and second samples of an underlying data from respective first and second sample periods and which correspond to respective first and second sensors, a phase control value may have first and second values during respective first and second sample periods. The phase control value may be a control value for a sample clock signal. The circuit may also determine a difference in the phase control value between the first value and the second value. The circuit may then digitally interpolate the first and second samples to produce a phase shifted first and second samples where the digital interpolation of at least one of the first and second samples mat be at least in part based on the difference in the phase control value to compensate for a phase misalignment between the first sample and the second sample.

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