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公开(公告)号：US08837075B2
公开(公告)日：2014-09-16
申请号：US13662829
申请日：2012-10-29
Applicant: Seagate Technology LLC
Inventor： Jorge Vicente Hanchi , Dian Song , John Stuart Wright , Andrew D. White
CPC classification number: G11B5/582 , G11B5/3133 , G11B5/40 , G11B5/5552 , G11B5/6005 , G11B5/6064
Abstract: A head assembly including one or more transducer elements for controlling head-media spacing is disclosed. The assembly includes detection circuitry configured to receive an input detection signal responsive to the spacing between the head and the data storage media and provide an output measure indicative of the head-media spacing. The output signal is utilized by control circuitry to provide a control input to one of a plurality of transducer elements on the head to protrude a localized portion of the head to adjust head-media spacing.
Abstract translation: 公开了一种包括一个或多个用于控制头部 - 媒体间隔的换能器元件的头组件。 组件包括检测电路，其被配置为响应于头部和数据存储介质之间的间隔接收输入检测信号，并提供指示头部 - 介质间隔的输出量度。 输出信号由控制电路用于向头部上的多个换能器元件中的一个提供控制输入，以突出头部的局部部分以调节头部 - 介质间隔。
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Patent Agency Ranking
公开(公告)号：US20130271889A1
公开(公告)日：2013-10-17
申请号：US13914379
申请日：2013-06-10
Applicant: Seagate Technology LLC
Inventor： Michael Christopher Kautzky , Charles Everett Hawkinson , Daniel Paul Burbank , John Stuart Wright
IPC: H02H3/08 , H01L41/257
CPC classification number: H02H3/08 , G11B5/4826 , G11B5/4873 , G11B5/6005 , H01L41/1132 , H01L41/257 , H01L41/338 , Y10T29/42
Abstract: A system for poling piezoelectric devices comprises a plurality of thin-film components, a plurality of piezoelectric devices, a poling pad for poling the piezoelectric devices, a plurality of traces, and a plurality of current-limiting elements. The thin-film components are separated by dice lanes to form an array, and the piezoelectric devices are formed on the thin-film components. The traces connect the piezoelectric devices across the dice lanes in parallel to the poling pad. Each current-limiting element is connected in series with one of the piezoelectric devices, in order to limit current to individual piezoelectric devices that experience current-related failure.
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公开(公告)号：US20130063834A1
公开(公告)日：2013-03-14
申请号：US13662829
申请日：2012-10-29
Applicant: Seagate Technology LLC
Inventor： Jorge Vicente Hanchi , Dian Song , John Stuart Wright , Andrew D. White
CPC classification number: G11B5/582 , G11B5/3133 , G11B5/40 , G11B5/5552 , G11B5/6005 , G11B5/6064
Abstract: A head assembly including one or more transducer elements for controlling head-media spacing is disclosed. The assembly includes detection circuitry configured to receive an input detection signal responsive to the spacing between the head and the data storage media and provide an output measure indicative of the head-media spacing. The output signal is utilized by control circuitry to provide a control input to one of a plurality of transducer elements on the head to protrude a localized portion of the head to adjust head-media spacing.
Abstract translation: 公开了一种包括一个或多个用于控制头部 - 媒体间隔的换能器元件的头组件。 组件包括检测电路，其被配置为响应于头部和数据存储介质之间的间隔接收输入检测信号，并提供指示头部 - 介质间隔的输出量度。 输出信号由控制电路用于向头部上的多个换能器元件中的一个提供控制输入，以突出头部的局部部分以调节头部 - 介质间隔。
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公开(公告)号：US20130026883A1
公开(公告)日：2013-01-31
申请号：US13633004
申请日：2012-10-01
Applicant: Seagate Technology LLC
Inventor： Michael Christopher Kautzky , Charles Everett Hawkinson , Daniel Paul Burbank , John Stuart Wright
IPC: H01L41/22
CPC classification number: H02H3/08 , G11B5/4826 , G11B5/4873 , G11B5/6005 , H01L41/1132 , H01L41/257 , H01L41/338 , Y10T29/42
Abstract: A system for poling piezoelectric devices comprises a plurality of thin-film components, a plurality of piezoelectric devices, a poling pad for poling the piezoelectric devices, a plurality of traces, and a plurality of current-limiting elements. The thin-film components are separated by dice lanes to form an array, and the piezoelectric devices are formed on the thin-film components. The traces connect the piezoelectric devices across the dice lanes in parallel to the poling pad. Each current-limiting element is connected in series with one of the piezoelectric devices, in order to limit current to individual piezoelectric devices that experience current-related failure.
Abstract translation: 用于极化压电装置的系统包括多个薄膜部件，多个压电装置，用于极化压电装置的极化垫，多个迹线和多个限流元件。 薄膜部件通过骰子线分隔开形成阵列，并且压电元件形成在薄膜部件上。 迹线将压电元件跨过骰子通道平行于极化垫。 每个限流元件与压电器件之一串联连接，以便将电流限制到经历电流相关故障的各个压电器件。
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公开(公告)号：US08937790B2
公开(公告)日：2015-01-20
申请号：US13914379
申请日：2013-06-10
Applicant: Seagate Technology LLC
Inventor： Michael Christopher Kautzky , Charles Everett Hawkinson , Daniel Paul Burbank , John Stuart Wright
IPC: G11B5/60
CPC classification number: H02H3/08 , G11B5/4826 , G11B5/4873 , G11B5/6005 , H01L41/1132 , H01L41/257 , H01L41/338 , Y10T29/42
Abstract: A system for poling piezoelectric devices comprises a plurality of thin-film components, a plurality of piezoelectric devices, a poling pad for poling the piezoelectric devices, a plurality of traces, and a plurality of current-limiting elements. The thin-film components are separated by dice lanes to form an array, and the piezoelectric devices are formed on the thin-film components. The traces connect the piezoelectric devices across the dice lanes in parallel to the poling pad. Each current-limiting element is connected in series with one of the piezoelectric devices, in order to limit current to individual piezoelectric devices that experience current-related failure.
Abstract translation: 用于极化压电装置的系统包括多个薄膜部件，多个压电装置，用于极化压电装置的极化垫，多个迹线和多个限流元件。 薄膜部件通过骰子线分隔开形成阵列，并且压电元件形成在薄膜部件上。 迹线将压电元件跨过骰子通道平行于极化垫。 每个限流元件与压电器件之一串联连接，以便将电流限制到经历电流相关故障的各个压电器件。
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公开(公告)号：US08477456B2
公开(公告)日：2013-07-02
申请号：US13633004
申请日：2012-10-01
Applicant: Seagate Technology LLC
Inventor： Michael Christopher Kautzky , Charles Everett Hawkinson , Daniel Paul Burbank , John Stuart Wright
IPC: G11B5/60
CPC classification number: H02H3/08 , G11B5/4826 , G11B5/4873 , G11B5/6005 , H01L41/1132 , H01L41/257 , H01L41/338 , Y10T29/42
Abstract: A system for poling piezoelectric devices comprises a plurality of thin-film components, a plurality of piezoelectric devices, a poling pad for poling the piezoelectric devices, a plurality of traces, and a plurality of current-limiting elements. The thin-film components are separated by dice lanes to form an array, and the piezoelectric devices are formed on the thin-film components. The traces connect the piezoelectric devices across the dice lanes in parallel to the poling pad. Each current-limiting element is connected in series with one of the piezoelectric devices, in order to limit current to individual piezoelectric devices that experience current-related failure.
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