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公开(公告)号:US10580468B2
公开(公告)日:2020-03-03
申请号:US15720115
申请日:2017-09-29
Applicant: Seagate Technology LLC
Inventor: Andrew Michael Kowles , Mark Gaertner , Xiong Liu , WenXiang Xie , Kai Yang , Jiangnan Lin
IPC: G06F12/00 , G11C7/22 , G11B5/31 , G11C11/409 , G06F12/0871 , G02B3/10
Abstract: In accordance with one implementation, a method for reducing cache service time includes determining an access time parameter associated with movement of a read/write head to an access location for each of a plurality of contiguous cache storage segments and dynamically selecting one of the plurality of contiguous cache storage segments to store data based on the determined access time parameter.
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公开(公告)号:US20190102307A1
公开(公告)日:2019-04-04
申请号:US15719957
申请日:2017-09-29
Applicant: Seagate Technology LLC
Inventor: Andrew Michael Kowles , Xiong Liu , Mark Gaertner , Kai Yang , WenXiang Xie , Jiangnan Lin
IPC: G06F12/0871 , G06F12/0875 , G06F12/0811
Abstract: In accordance with one implementation, a method for mitigating cache transfer time entails reading data into memory from at least two consecutive elliptical data tracks in a main store region of data storage and writing the data read from the at least two consecutive elliptical data tracks to a spiral data track within a cache storage region.
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公开(公告)号:US20150169466A1
公开(公告)日:2015-06-18
申请号:US14633708
申请日:2015-02-27
Applicant: Seagate Technology LLC
Inventor: Mark Gaertner , Mark Alan Heath
IPC: G06F12/10
CPC classification number: G06F12/0284 , G06F7/785 , G06F2212/657
Abstract: A method for managing a memory stack provides mapping a part of the memory stack to a span of fast memory and a part of the memory stack to a span of slow memory, wherein the fast memory provides access speed substantially higher than the access speed provided by the slow memory.
Abstract translation: 用于管理存储器堆栈的方法提供将存储器堆栈的一部分映射到快速存储器的一部分和存储器堆栈的一部分到慢存储器的跨度,其中快速存储器提供的访问速度显着高于由 缓慢的记忆
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公开(公告)号:US20160055053A1
公开(公告)日:2016-02-25
申请号:US14467983
申请日:2014-08-25
Applicant: Seagate Technology LLC
Inventor: Jon D. Trantham , Brian T. Edgar , Mark Gaertner , Bruce Buch
CPC classification number: G06F11/1004 , G06F11/1012 , H03M13/09 , H03M13/096
Abstract: Certain exemplary aspects of the present disclosure are directed towards methods and apparatuses in which logic circuitry generates an error detection code based on user data received from a host, and further generates a first set of check bits, to be written to the non-volatile memory circuit in conjunction with the user data, by combining the error detection code with a hashed data address of the user data. In some embodiments, the check bits associated with the user data providing verification that the user data was written in the appropriate physical block address of the non-volatile memory circuit.
Abstract translation: 本公开的某些示例性方面涉及其中逻辑电路基于从主机接收的用户数据生成错误检测码的方法和装置,并进一步产生要写入非易失性存储器的第一组校验位 通过将错误检测码与用户数据的散列数据地址组合在一起,与用户数据相结合。 在一些实施例中,与用户数据相关联的校验位提供用户数据被写入非易失性存储器电路的适当物理块地址中的验证。
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公开(公告)号:US10579533B2
公开(公告)日:2020-03-03
申请号:US15719957
申请日:2017-09-29
Applicant: Seagate Technology LLC
Inventor: Andrew Michael Kowles , Xiong Liu , Mark Gaertner , Kai Yang , WenXiang Xie , Jiangnan Lin
IPC: G06F3/06 , G06F12/0871 , G06F12/0875 , G06F12/0811
Abstract: In accordance with one implementation, a method for mitigating cache transfer time entails reading data into memory from at least two consecutive elliptical data tracks in a main store region of data storage and writing the data read from the at least two consecutive elliptical data tracks to a spiral data track within a cache storage region.
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公开(公告)号:US09244860B2
公开(公告)日:2016-01-26
申请号:US14633708
申请日:2015-02-27
Applicant: Seagate Technology LLC
Inventor: Mark Gaertner , Mark Alan Heath
CPC classification number: G06F12/0284 , G06F7/785 , G06F2212/657
Abstract: A method for managing a memory stack provides mapping a part of the memory stack to a span of fast memory and a part of the memory stack to a span of slow memory, wherein the fast memory provides access speed substantially higher than the access speed provided by the slow memory.
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公开(公告)号:US11243887B2
公开(公告)日:2022-02-08
申请号:US16802121
申请日:2020-02-26
Applicant: Seagate Technology LLC
Inventor: Andrew Michael Kowles , Xiong Liu , Mark Gaertner , Kai Yang , WenXiang Xie , Jiangnan Lin
IPC: G06F12/0866 , G06F12/0871 , G06F12/0875 , G06F12/0811 , G06F3/06
Abstract: In accordance with one implementation, a method for mitigating cache transfer time entails reading data into memory from at least two consecutive elliptical data tracks in a main store region of data storage and writing the data read from the at least two consecutive elliptical data tracks to a spiral data track within a cache storage region.
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公开(公告)号:US10310923B1
公开(公告)日:2019-06-04
申请号:US14471981
申请日:2014-08-28
Applicant: Seagate Technology LLC
Inventor: Jeffrey Vincent DeRosa , Jon David Trantham , Mark Gaertner
IPC: G06F11/07
Abstract: Systems and methods are disclosed for probabilistic aging command sorting, including adjusting an execution order for a command based on a probability of the command reaching a time out threshold. Various example embodiments are directed to selecting a command for execution from a queue of commands awaiting execution, in which the commands have non-uniform attributes influencing their selection and a time limit within which to execute them. In some embodiments, an apparatus may comprise a circuit configured to calculate a first estimated access time to execute a selected command from a command queue, modify the first estimated access time based on a probability of the selected command reaching a time-out age threshold to determine a time out-adjusted access time, and execute the selected command in an order based on the time out-adjusted access time.
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公开(公告)号:US20190103146A1
公开(公告)日:2019-04-04
申请号:US15720115
申请日:2017-09-29
Applicant: Seagate Technology LLC
Inventor: Andrew Michael Kowles , Mark Gaertner , Xiong Liu , WenXiang Xie , Kai Yang , Jiangnan Lin
IPC: G11C7/22 , G06F12/0871 , G11C11/409 , G11B5/31
Abstract: In accordance with one implementation, a method for reducing cache service time includes determining an access time parameter associated with movement of a read/write head to an access location for each of a plurality of contiguous cache storage segments and dynamically selecting one of the plurality of contiguous cache storage segments to store data based on the determined access time parameter.
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公开(公告)号:US10180792B1
公开(公告)日:2019-01-15
申请号:US14701447
申请日:2015-04-30
Applicant: Seagate Technology LLC
Inventor: Mark Gaertner , James D Sawin
Abstract: Data storage devices may store selected data received from a data source to a buffer memory. The selected data may be copied from the buffer to a non-volatile memory configured for sequential storage. The selected data may then be copied from the buffer to a solid state memory, such as dynamic random access memory. The selected data may be copied from the solid state memory to a main store, such as a magnetic disc memory. If the selected data cannot be found in the solid state memory, the selected data in the non-volatile memory can be copied to the main store.
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