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    Bit line selection circuit
    1.
    发明授权
    Bit line selection circuit 失效
    位线选择电路

    公开(公告)号：US5781487A

    公开(公告)日：1998-07-14

    申请号：US637917

    申请日：1996-04-26

    Applicant: Seong Jin Jang

    Inventor： Seong Jin Jang

    IPC: G11C11/409 ,  G11C7/18 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4091 ,  G11C11/4097 ,  G11C7/00

    CPC classification number: G11C7/18 ,  G11C11/4091 ,  G11C11/4097

    Abstract: An improved bit line selection circuit which is capable of preventing power consumption of Vpp by delaying an external signal for a predetermined time, first turning off the NMOS transistor connected to Vcc, turning on the PMOS transistor connected to Vpp, and preventing a formation of a current path from Vpp to Vcc, which incudes a control signal generation unit for generating a control signal by operating an external signal inputted thereto through an input node, the control signal generation unit being symmetrical; first and second bit line selection signal generation unit for generating a bit line selection signal of Vpp level in accordance with a control of the control signal generation unit; and an electric charge charging unit for charging a part of electric charges when a selection signal of the first or second bit line selection signal is discharged from Vpp to Vcc, recycling electric charge which is charged when selecting a bit line, and precharging a bit line selection signal.

    Abstract translation: 一种改进的位线选择电路，其能够通过将外部信号延迟预定时间来防止Vpp的功率消耗，首先关闭连接到Vcc的NMOS晶体管，导通连接到Vpp的PMOS晶体管，并且防止形成 从Vpp到Vcc的电流路径，其包括控制信号生成单元，用于通过通过输入节点操作输入的外部信号来产生控制信号，所述控制信号生成单元是对称的; 第一和第二位线选择信号生成单元，用于根据控制信号生成单元的控制产生Vpp电平的位线选择信号; 以及电荷充电单元，用于当第一或第二位线选择信号的选择信号从Vpp放电到Vcc时对一部分电荷充电，再循环在选择位线时充电的电荷，并且对位线进行预充电 选择信号。

    Methods and circuits for generating reference voltage
    2.
    发明授权
    Methods and circuits for generating reference voltage 有权
    产生参考电压的方法和电路

    公开(公告)号：US08344792B2

    公开(公告)日：2013-01-01

    申请号：US11191376

    申请日：2005-07-28

    Applicant: Seong Jin Jang

    Inventor： Seong Jin Jang

    IPC: G05F1/10

    CPC classification number: G05F3/02 ,  G11C5/147

    Abstract: A circuit for generating a reference voltage includes a first reference voltage generating circuit disposed outside a chip and a second reference voltage generating circuit disposed inside the chip. The first and second reference voltage generating circuits output first and second reference voltages to first and second output terminals, respectively. The second reference voltage generating circuit includes at least one pull-up resistor and at least one pull-down resistor. The pull-up resistor is coupled between a first node where an internal power supply voltage is coupled and the second output terminal. The pull-down resistor is coupled between a second node and the second output terminal, wherein a voltage at the second node is relatively lower than a voltage at the first node. A third reference voltage is outputted from a node where the first output terminal is coupled to the second output terminal.

    Abstract translation: 用于产生参考电压的电路包括设置在芯片外部的第一参考电压发生电路和设置在芯片内部的第二参考电压产生电路。 第一和第二参考电压产生电路分别将第一和第二参考电压输出到第一和第二输出端。 第二参考电压产生电路包括至少一个上拉电阻和至少一个下拉电阻。 上拉电阻耦合在耦合内部电源电压的第一节点和第二输出端子之间。 下拉电阻器耦合在第二节点和第二输出端子之间，其中第二节点处的电压相对低于第一节点处的电压。 从第一输出端耦合到第二输出端的节点输出第三参考电压。

    Memory device with separate read and write gate voltage controls
    3.
    发明授权
    Memory device with separate read and write gate voltage controls 有权
    具有独立读和写电压控制的存储器件

    公开(公告)号：US07619935B2

    公开(公告)日：2009-11-17

    申请号：US11680886

    申请日：2007-03-01

    Applicant: Kyoung Ho Kim ,  Seong Jin Jang

    Inventor： Kyoung Ho Kim ,  Seong Jin Jang

    IPC: G11C7/10 ,  G11C7/00

    CPC classification number: G11C7/18 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/4093 ,  G11C11/4097 ,  G11C2207/002

    Abstract: A circuit and method are provided for controlling the gate voltage of a transistor acting between local and global input/output lines of a memory device, the circuit including a local input/output line, a local from/to global input/output multiplexer in signal communication with the local input/output line, a global input/output line in signal communication with the local from/to global input/output multiplexer, and a local from/to global input/output controller having an input node and an output node, the input node disposed for receiving a signal indicative of an input or output operation, and the output node in signal communication with a gate of the local from/to global input/output multiplexer for providing a gate signal of a first or second level in the presence of the output operation, and a gate signal of a third level in the presence of the input operation.

    Abstract translation: 提供了一种电路和方法，用于控制在存储器件的局部和全局输入/输出线之间起作用的晶体管的栅极电压，该电路包括本地输入/输出线，本地输入/输出多路复用器的本地信号 与本地输入/输出线的通信，与本地从/到全局输入/输出多路复用器进行信号通信的全局输入/输出线，以及具有输入节点和输出节点的本地输入/输出控制器， 所述输入节点被设置用于接收指示输入或输出操作的信号，并且所述输出节点与所述本地输入/输出多路复用器的门相信号通信，以在所述输入/输出多路复用器中提供第一或第二电平的门信号 在存在输入操作的情况下存在输出操作和第三级的门信号。

    Dynamic random access memory having self-test function
    5.
    发明授权
    Dynamic random access memory having self-test function 失效
    具有自检功能的动态随机存取存储器

    公开(公告)号：US5640354A

    公开(公告)日：1997-06-17

    申请号：US636003

    申请日：1996-04-22

    Applicant: Seong Jin Jang ,  Young-Hyun Jun ,  Jae Sik Lee

    Inventor： Seong Jin Jang ,  Young-Hyun Jun ,  Jae Sik Lee

    IPC: G11C29/00 ,  G11C11/401 ,  G11C11/407 ,  G11C29/12 ,  G11C29/44 ,  G11C29/46 ,  G11C11/34

    CPC classification number: G11C29/46 ,  G11C29/44

    Abstract: An improved DRAM having a self-test function capable of performing a self-test function in a fast page mode in accordance with a transition of a column address in accordance with an interior clock signal without a toggle of a column address strobe signal, which includes an entry/exit control unit for generating a self-test entry signal in accordance with a combination a predetermined address signal and an external synchronous signal; a signal transition detection unit for detecting a transition of a self-test entry signal and a word line enable signal and for outputting a transition detection signal; a counter for counting an interior clock signal outputted in accordance with a transition detection signal; a data generating and comparison unit for writing and reading a test data without a toggle of the external synchronous signal comparing the read test data with the generated test data; and an error and end detection unit for generating an error flag and end flag.

    Abstract translation: 一种具有自检功能的改进DRAM，其能够根据内部时钟信号而根据列地址的转换而在快速页模式下执行自检功能，而不需要列地址选通信号的切换，该DRAM地址选通信号包括 入口/出口控制单元，用于根据预定地址信号和外部同步信号的组合产生自检入口信号; 信号转换检测单元，用于检测自检入场信号和字线使能信号的转变，并输出转换检测信号; 计数器，用于对根据转换检测信号输出的内部时钟信号进行计数; 数据生成和比较单元，用于在不读取测试数据与所生成的测试数据的外部同步信号的切换的情况下写入和读取测试数据; 以及用于产生错误标志和结束标志的错误和结束检测单元。

    MEMORY DEVICE WITH SEPARATE READ AND WRITE GATE VOLTAGE CONTROLS
    7.
    发明申请
    MEMORY DEVICE WITH SEPARATE READ AND WRITE GATE VOLTAGE CONTROLS 有权
    具有独立读和写门控电压的存储器件

    公开(公告)号：US20080037333A1

    公开(公告)日：2008-02-14

    申请号：US11680886

    申请日：2007-03-01

    Applicant: Kyoung Ho Kim ,  Seong Jin Jang

    Inventor： Kyoung Ho Kim ,  Seong Jin Jang

    IPC: G11C7/10

    CPC classification number: G11C7/18 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/4093 ,  G11C11/4097 ,  G11C2207/002

    Abstract: A circuit and method are provided for controlling the gate voltage of a transistor acting between local and global input/output lines of a memory device, the circuit including a local input/output line, a local from/to global input/output multiplexer in signal communication with the local input/output line, a global input/output line in signal communication with the local from/to global input/output multiplexer, and a local from/to global input/output controller having an input node and an output node, the input node disposed for receiving a signal indicative of an input or output operation, and the output node in signal communication with a gate of the local from/to global input/output multiplexer for providing a gate signal of a first or second level in the presence of the output operation, and a gate signal of a third level in the presence of the input operation.

    Abstract translation: 提供了一种电路和方法，用于控制在存储器件的局部和全局输入/输出线之间起作用的晶体管的栅极电压，该电路包括本地输入/输出线，本地输入/输出多路复用器的本地信号 与本地输入/输出线的通信，与本地从/到全局输入/输出多路复用器进行信号通信的全局输入/输出线，以及具有输入节点和输出节点的本地输入/输出控制器， 所述输入节点被设置用于接收指示输入或输出操作的信号，并且所述输出节点与所述本地输入/输出多路复用器的门相信号通信，以在所述输入/输出多路复用器中提供第一或第二电平的门信号 在存在输入操作的情况下存在输出操作和第三级的门信号。

    Column selection circuit
    8.
    发明授权
    Column selection circuit 失效
    列选择电路

    公开(公告)号：US5892722A

    公开(公告)日：1999-04-06

    申请号：US126737

    申请日：1998-07-31

    Applicant: Seong Jin Jang ,  Young Hyun Jun ,  Sung Wook Kim ,  Tae Hoon Kim

    Inventor： Seong Jin Jang ,  Young Hyun Jun ,  Sung Wook Kim ,  Tae Hoon Kim

    IPC: G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C11/4096 ,  G11C7/00

    CPC classification number: G11C7/10 ,  G11C11/4096

    Abstract: A column selection circuit is disclosed, in which a layout area is minimized by reducing the number of data bus lines and sensing speed characteristic is improved by reducing sensing time of a bit line. In a memory for transmitting data stored in a memory cell to a main sensing amplifier through a bit line and a bit bar line and storing the data output from the main sensing amplifier in the memory cell through the bit line and the bit bar line, the column selection circuit includes an equalizer for equalizing the bit line and the bit bar line, a bit line sensing amplifier for compensating signal voltage levels of the bit line and the bit bar line as a word line is selected, first and second enable signal output portions for outputting enable signals to operate the bit line sensing amplifier, a data bus line and a data bus bar line for transmitting the data transmitted to the bit line and the bit bar line from the memory cell to the main sensing amplifier, and transmitting the data output from the main sensing amplifier to the bit line and the bit bar line, a data transmission portion for selectively transmitting the data of the data bus line and data bus bar line and the data of the bit line and bit bar line between the respective lines in response to a column selection signal, a control signal for reading and a write enable signal, and a precharge level adjusting portion for adjusting precharge level of the data bus line and the data bus bar line.

    Abstract translation: 公开了一种列选择电路，其中通过减少数据总线的数量使布局面积最小化，并且通过减少位线的检测时间来提高感测速度特性。 在用于通过位线和位线将存储在存储单元中的数据存储到主感测放大器的存储器中，并且通过位线和位线将存储器单元中输出的从主感测放大器输出的数据存储起来， 列选择电路包括用于均衡位线和位线的均衡器，选择用于补偿位线和位线的信号电压电平的位线检测放大器，第一和第二使能信号输出部分 用于输出用于操作位线感测放大器的使能信号，数据总线和数据总线条线，用于将从存储器单元发送到位线和位线的数据发送到主感测放大器，并且发送数据 从主感测放大器输出到位线和位线，数据传输部分，用于选择性地发送数据总线和数据总线条的数据以及b的数据 响应于列选择信号，用于读取的控制信号和写使能信号，在各行之间的行和位条线以及用于调整数据总线和数据总线条线的预充电电平的预充电电平调整部分 。

    Circuit precharging DRAM bit line
    9.
    发明授权
    Circuit precharging DRAM bit line 失效
    电路预充电DRAM位线

    公开(公告)号：US08194484B2

    公开(公告)日：2012-06-05

    申请号：US12787567

    申请日：2010-05-26

    Applicant: Cheon An Lee ,  Seong Jin Jang ,  Jong Pil Son ,  Sang Joon Hwang

    Inventor： Cheon An Lee ,  Seong Jin Jang ,  Jong Pil Son ,  Sang Joon Hwang

    IPC: G11C7/00

    CPC classification number: G11C11/4094

    Abstract: A bit line pre-charge circuit for a dynamic random access memory (DRAM) uses a charge sharing scheme. The pre-charge circuit includes switching elements disposed between a power voltage node and an output node, capacitors connected between intermediate nodes and ground. The switching elements being operated by successively activated control signals to effectively charge a bit line pair to one half a power voltage using charge sharing between the capacitors.

    Abstract translation: 用于动态随机存取存储器（DRAM）的位线预充电电路使用电荷共享方案。 预充电电路包括设置在电源电压节点和输出节点之间的开关元件，连接在中间节点和地之间的电容器。 开关元件由连续激活的控制信号操作，以使用电容器之间的电荷共享来有效地将位线对充电到电源电压的一半。

    MOSFET having tapered gate electrode
    10.
    发明授权
    MOSFET having tapered gate electrode 失效
    MOSFET具有锥形栅电极

    公开(公告)号：US5834816A

    公开(公告)日：1998-11-10

    申请号：US816009

    申请日：1997-03-10

    Applicant: Seong Jin Jang

    Inventor： Seong Jin Jang

    IPC: H01L29/78 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L29/423 ,  H01L29/76 ,  H01L23/48 ,  H01L29/94 ,  H01L31/062

    CPC classification number: H01L29/66606 ,  H01L21/28518 ,  H01L21/76889 ,  H01L29/42376 ,  H01L2924/0002 ,  Y10S148/117

    Abstract: A MOSFET comprising a gate oxide layer on a silicon substrate, a polysilicon gate formed on the gate oxide layer, the length of which gradually widens going from bottom to top, a side gate oxide layer formed by an oxidation process surrounding the polysilicon gate, the side gate oxide layer also gradually widening from bottom to top, a source/drain region beside the gate oxide layer, a connection element having a stacked structure of a polysilicon and/or polycide layer on the field oxide, a doped polysilicon side wall beside the side gate oxide layer and making electric connection between the source/drain region and the connection element.

    Abstract translation: 一种MOSFET，包括在硅衬底上的栅极氧化层，形成在栅极氧化物层上的多晶硅栅极，其长度从底部到顶部逐渐变宽，通过围绕多晶硅栅极的氧化工艺形成的侧栅氧化层， 侧栅极氧化物层也从底部向上逐渐变宽，在栅极氧化物层旁边的源极/漏极区域，在场氧化物上具有多晶硅和/或多晶硅化物层的堆叠结构的连接元件，旁边的掺杂多晶硅侧壁 并且在源极/漏极区域和连接元件之间形成电连接。

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