公开(公告)号：US10903838B1

公开(公告)日：2021-01-26

申请号：US16656867

申请日：2019-10-18

Applicant: Silicon Laboratories Inc.

Inventor： Brian Taylor Brunn ,  Paul Ivan Zavalney ,  Adrianus Josephus Bink ,  Chester Yu

IPC: G06F1/08 ,  G06F1/324 ,  H03K19/00

Abstract: An integrated circuit includes a clock management unit that selectively provides a clock signal, an energy management circuit that provides an internal power supply voltage to an internal voltage rail in response to an external power supply voltage, and has a capacitor coupled between the internal voltage rail and a reference voltage terminal, and a clocked digital circuit that is coupled to the internal voltage rail and the reference voltage terminal and operates in synchronism with the clock signal. The clock management unit provides the clock signal at a first frequency during a standby state, continuously at a second frequency higher than the first frequency during an active state, and during a first clock cycle following an end of the standby state while suppressing the clock signal during at least one subsequent clock cycle during a transition state between the standby state and the active state.

公开(公告)号：US20220309191A1

公开(公告)日：2022-09-29

申请号：US17210823

申请日：2021-03-24

Applicant: Silicon Laboratories Inc.

Inventor： Brian Taylor Brunn

IPC: G06F21/72 ,  G06F1/08

Abstract: In one embodiment, an apparatus includes: a clock generator to receive a reference clock signal and generate a first clock signal using the reference clock signal; a counter coupled to the clock generator to maintain a first count regarding a number of cycles of the first clock signal; and a controller coupled to the counter. The controller may be configured to detect a potential security violation when the first count varies from a predetermined value.

公开(公告)号：US11061452B2

公开(公告)日：2021-07-13

申请号：US16570581

申请日：2019-09-13

Applicant: Silicon Laboratories Inc.

Inventor： Brian Taylor Brunn ,  Rui Deng

IPC: G06F1/3203 ,  G06F1/20 ,  G06F1/3206

Abstract: An integrated circuit includes a digital circuit and an energy management circuit. The digital circuit operates with an internal power supply voltage in synchronism with a clock signal and comprises complementary metal-oxide-semiconductor (CMOS) transistors. The energy management circuit has an input for receiving an external power supply voltage and an output for providing the internal power supply voltage. The energy management circuit is thermally coupled to the digital circuit and sets the internal power supply voltage to a nominal voltage when a temperature of the digital circuit is greater than a boost temperature. The energy management circuit boosts the internal power supply voltage to a boosted voltage greater than the nominal voltage when the temperature of the digital circuit is less than the boost temperature.

公开(公告)号：US20240095407A1

公开(公告)日：2024-03-21

申请号：US18521023

申请日：2023-11-28

Applicant: Silicon Laboratories Inc.

Inventor： Brian Taylor Brunn

IPC: G06F21/72 ,  G06F1/08

CPC classification number: G06F21/725 ,  G06F1/08

Abstract: In one embodiment, an apparatus includes: a clock generator to receive a reference clock signal and generate a first clock signal using the reference clock signal; a counter coupled to the clock generator to maintain a first count regarding a number of cycles of the first clock signal; and a controller coupled to the counter. The controller may be configured to detect a potential security violation when the first count varies from a predetermined value.

公开(公告)号：US20210081010A1

公开(公告)日：2021-03-18

申请号：US16570581

申请日：2019-09-13

Applicant: Silicon Laboratories Inc.

Inventor： Brian Taylor Brunn ,  Rui Deng

IPC: G06F1/20 ,  G06F1/3206

Abstract: An integrated circuit includes a digital circuit and an energy management circuit. The digital circuit operates with an internal power supply voltage in synchronism with a clock signal and comprises complementary metal-oxide-semiconductor (CMOS) transistors. The energy management circuit has an input for receiving an external power supply voltage and an output for providing the internal power supply voltage. The energy management circuit is thermally coupled to the digital circuit and sets the internal power supply voltage to a nominal voltage when a temperature of the digital circuit is greater than a boost temperature. The energy management circuit boosts the internal power supply voltage to a boosted voltage greater than the nominal voltage when the temperature of the digital circuit is less than the boost temperature.

公开(公告)号：US11886621B2

公开(公告)日：2024-01-30

申请号：US17210823

申请日：2021-03-24

Applicant: Silicon Laboratories Inc.

Inventor： Brian Taylor Brunn

IPC: G06F21/72 ,  G06F1/08

CPC classification number: G06F21/725 ,  G06F1/08

Abstract: In one embodiment, an apparatus includes: a clock generator to receive a reference clock signal and generate a first clock signal using the reference clock signal; a counter coupled to the clock generator to maintain a first count regarding a number of cycles of the first clock signal; and a controller coupled to the counter. The controller may be configured to detect a potential security violation when the first count varies from a predetermined value.