公开(公告)号：US20250031094A1

公开(公告)日：2025-01-23

申请号：US18236184

申请日：2023-08-21

Applicant: Silicon Laboratories Inc.

Inventor： Hendricus De Ruijter ,  Terry Dickey ,  Wentao Li ,  Bryan Murawski ,  Marius Munder

IPC: H04W28/06 ,  H04W28/08 ,  H04W28/10

Abstract: A technique for adding a new information rate to a legacy physical interface of a communications system includes using a rate switch packet including a distinct rate select start-of-frame delimiter that indicates a newly defined physical interface packet. The rate switch packet uses the same modulation scheme as a base rate packet (e.g., a packet using an information rate defined by a standard communications protocol) and the same preamble pattern as the base rate packet. The preamble length of the rate switch packet can be the same as or different from the preamble length of the base rate packet. An embodiment uses antenna diversity by selecting the antenna in the rate switch packet and using the selected antenna to receive an adjusted rate packet. Additional rate switch start-of-frame delimiters can be used to indicate more than one adjusted rate packet, e.g., to support multiple adjusted information rates.

公开(公告)号：US08666349B2

公开(公告)日：2014-03-04

申请号：US13888745

申请日：2013-05-07

Applicant: Silicon Laboratories Inc.

Inventor： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

IPC: H04B1/10

CPC classification number: H03J3/02 ,  H04B15/02 ,  H04B2215/064 ,  H04B2215/065

Abstract: A radio frequency (RF) receiver comprises an analog receiver, a digital signal processor, a clock synthesizer, and a microcontroller. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital signal processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, and a signal output for providing an IF output signal. The clock synthesizer has an input for receiving a clock control signal, and an output for providing the clock signal. The a microcontroller has an input for receiving a channel selection signal, wherein the microcontroller provides the clock control signal to control a frequency of the clock signal dynamically in response to a channel selection input to place a sub-harmonic at a tolerable frequency of a selected channel.

Abstract translation: 射频（RF）接收机包括模拟接收机，数字信号处理器，时钟合成器和微控制器。 模拟接收机具有用于接收RF输入信号的输入端和用于提供数字中频（IF）信号的输出端。 数字信号处理器具有用于接收数字IF信号的第一输入端，用于接收时钟信号的第二输入端和用于提供IF输出信号的信号输出端。 时钟合成器具有用于接收时钟控制信号的输入端和用于提供时钟信号的输出端。 微控制器具有用于接收频道选择信号的输入，其中微控制器提供时钟控制信号，以响应于信道选择输入动态地控制时钟信号的频率，以将子谐波放置在所选择的可容许频率 渠道。