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    Calibration of an interpolative divider using a virtual phase-locked loop
    1.
    发明授权
    Calibration of an interpolative divider using a virtual phase-locked loop 有权

    公开(公告)号：US10833682B1

    公开(公告)日：2020-11-10

    申请号：US16582266

    申请日：2019-09-25

    Applicant: Silicon Laboratories Inc.

    Inventor： Timothy A. Monk ,  Douglas F. Pastorello

    IPC: H03L7/06 ,  H03L7/081 ,  H03L7/197 ,  H03L7/093

    Abstract: A clock generator includes an interpolative divider including a phase interpolator and a multi-modulus divider. The interpolative divider is configured to generate an output clock signal based on a clock signal, a control code, and a phase interpolator calibration signal. The clock generator includes a calibration circuit configured to generate the phase interpolator calibration signal based on the clock signal, the output clock signal and a phase interpolator code. The calibration circuit includes a phase-locked loop configured to generate a digital phase error signal based on a reference timestamp signal and a timestamp signal based on the clock signal and the output clock signal. The calibration circuit includes an adaptive loop configured to generate the phase interpolator calibration signal based on the digital phase error signal.

    Spur canceller with multiplier-less correlator
    2.
    发明授权
    Spur canceller with multiplier-less correlator 有权

    公开(公告)号：US10680622B2

    公开(公告)日：2020-06-09

    申请号：US16143711

    申请日：2018-09-27

    Applicant: Silicon Laboratories Inc.

    Inventor： Timothy A. Monk ,  Rajesh Thirugnanam

    IPC: H03L7/06 ,  H03L7/085 ,  G04F10/00

    Abstract: A spur cancellation circuit uses low cost multipliers in a correlation circuit. Each low cost multiplier multiplies a value of a sense node by a representation of a sinusoid and supplies a multiplication result. A compare circuit compares the sinusoid to one or more threshold values and supplies a compare indication. A multiplexer selects between two or more inputs including a positive value of the sense node and a negative value of the sense node, based on the compare result. A single threshold at zero converts the sinusoid to a square wave and the multiplexer supplies either the positive value or the negative value, which is equivalent to multiplying the value at the sense node by 1 or −1 depending on the sign of the sinusoid. Two thresholds may be used to represent the sinusoid with three values, the positive value, the negative value, or zero.

    Spur cancellation for spur measurement
    3.
    发明授权
    Spur cancellation for spur measurement 有权

    公开(公告)号：US11095295B2

    公开(公告)日：2021-08-17

    申请号：US16018598

    申请日：2018-06-26

    Applicant: Silicon Laboratories Inc.

    Inventor： Timothy A. Monk ,  Rajesh Thirugnanam

    IPC: H03L7/093 ,  G01R29/26 ,  G04F10/00 ,  G01R31/317

    Abstract: A spur measurement system uses a first device with a spur cancellation circuit that cancel spurs responsive to a frequency control word identifying a spurious tone of interest. A device under test generates a clock signal and supplies the clock signal to the first device through an optional divider. The spur cancellation circuit in the first device generates sine and cosine weights at the spurious tone of interest as part of the spur cancellation process. A first magnitude of the spurious tone in a phase-locked loop in the first device is determined according to the sine and cosine weights and a second magnitude of the spurious tone in the clock signal is determined by the first magnitude divided by gains associated with the first device.

    SPUR CANCELLATION FOR SPUR MEASUREMENT
    4.
    发明申请
    SPUR CANCELLATION FOR SPUR MEASUREMENT 审中-公开

    公开(公告)号：US20190393881A1

    公开(公告)日：2019-12-26

    申请号：US16018598

    申请日：2018-06-26

    Applicant: Silicon Laboratories Inc.

    Inventor： Timothy A. Monk ,  Rajesh Thirugnanam

    IPC: H03L7/093 ,  G04F10/00 ,  G01R31/317 ,  G01R29/26

    Abstract: A spur measurement system uses a first device with a spur cancellation circuit that cancel spurs responsive to a frequency control word identifying a spurious tone of interest. A device under test generates a clock signal and supplies the clock signal to the first device through an optional divider. The spur cancellation circuit in the first device generates sine and cosine weights at the spurious tone of interest as part of the spur cancellation process. A first magnitude of the spurious tone in a phase-locked loop in the first device is determined according to the sine and cosine weights and a second magnitude of the spurious tone in the clock signal is determined by the first magnitude divided by gains associated with the first device.

    Correction for period error in a reference clock signal
    5.
    发明授权
    Correction for period error in a reference clock signal 有权

    公开(公告)号：US11316522B2

    公开(公告)日：2022-04-26

    申请号：US16901814

    申请日：2020-06-15

    Applicant: Silicon Laboratories Inc.

    Inventor： Aslamali A. Rafi ,  Timothy A. Monk ,  William Anker ,  Srisai Rao Seethamraju

    IPC: H03L7/099 ,  H03L7/08 ,  H03L7/197 ,  H03L7/14

    Abstract: A phase and frequency detector receives a reference clock signal with a period error and receives a feedback clock signal from a feedback divider. The feedback divider circuit divides a clock signal from a voltage controlled oscillator. The feedback divider divides by different divide values during odd and even cycles of the reference clock signal to cause the feedback clock signal to have a period error that substantially matches the period error of the reference clock signal. The divider values supplied to the feedback divider are determined, at least in part, by the period error of the reference clock signal.

    CORRECTION FOR PERIOD ERROR IN A REFERENCE CLOCK SIGNAL
    7.
    发明申请
    CORRECTION FOR PERIOD ERROR IN A REFERENCE CLOCK SIGNAL 有权

    公开(公告)号：US20210391864A1

    公开(公告)日：2021-12-16

    申请号：US16901814

    申请日：2020-06-15

    Applicant: Silicon Laboratories Inc.

    Inventor： Aslamali A. Rafi ,  Timothy A. Monk ,  William Anker ,  Srisai Rao Seethamraju

    IPC: H03L7/08 ,  H03L7/099 ,  H03L7/14 ,  H03L7/197

    Abstract: A phase and frequency detector receives a reference clock signal with a period error and receives a feedback clock signal from a feedback divider. The feedback divider circuit divides a clock signal from a voltage controlled oscillator. The feedback divider divides by different divide values during odd and even cycles of the reference clock signal to cause the feedback clock signal to have a period error that substantially matches the period error of the reference clock signal. The divider values supplied to the feedback divider are determined, at least in part, by the period error of the reference clock signal.

    SPUR CANCELLER WITH MULTIPLIER-LESS CORRELATOR
    8.
    发明申请
    SPUR CANCELLER WITH MULTIPLIER-LESS CORRELATOR 审中-公开

    公开(公告)号：US20200106447A1

    公开(公告)日：2020-04-02

    申请号：US16143711

    申请日：2018-09-27

    Applicant: Silicon Laboratories Inc.

    Inventor： Timothy A. Monk ,  Rajesh Thirugnanam

    IPC: H03L7/085

    Abstract: A spur cancellation circuit uses low cost multipliers in a correlation circuit. Each low cost multiplier multiplies a value of a sense node by a representation of a sinusoid and supplies a multiplication result. A compare circuit compares the sinusoid to one or more threshold values and supplies a compare indication. A multiplexer selects between two or more inputs including a positive value of the sense node and a negative value of the sense node, based on the compare result. A single threshold at zero converts the sinusoid to a square wave and the multiplexer supplies either the positive value or the negative value, which is equivalent to multiplying the value at the sense node by 1 or −1 depending on the sign of the sinusoid. Two thresholds may be used to represent the sinusoid with three values, the positive value, the negative value, or zero.

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