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1.发明公开公开(公告)号：US20240363183A1
公开(公告)日：2024-10-31
申请号：US18225654
申请日：2023-07-24
Applicant: Silicon Motion, Inc.
Inventor： Fu-Jen Shih
IPC: G11C29/12
CPC classification number: G11C29/1201 , G11C29/12005 , G11C2207/2254
Abstract: A method for calibrating a characteristic value of a signal processing device comprised in SerDes inside of an interface circuit of a memory controller includes: monitoring a current of a voltage of a test element to generate a process detection result by a monitor and calibration module; monitoring an environment temperature to generate a temperature monitored result by the monitor and calibration module; selecting a reference value subset from multiple reference value subsets as a preferred reference value subset for a calibration operation based on the process detection result and the temperature monitored result; and performing the calibration operation on the signal processing device by at least one calibration circuit of the monitor and calibration module according to the preferred reference value subset to adjust the characteristic value of the signal processing device.
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2.发明公开公开(公告)号：US20230168958A1
公开(公告)日：2023-06-01
申请号：US17948254
申请日：2022-09-20
Applicant: Silicon Motion, Inc.
Inventor： Fu-Jen Shih
CPC classification number: G06F11/0751 , H04L1/0016 , G06F11/0745
Abstract: An interface circuit includes a signal processing circuit configured to process a reception signal received from a host device and a transmission signal to be transmitted to the host device. The signal processing circuit includes multiple signal processing devices and a calibration device. The calibration device is coupled to the signal processing devices and configured to sequentially calibrate a characteristic value of each signal processing device in a calibration procedure.
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3.发明申请公开(公告)号：US20220029630A1
公开(公告)日：2022-01-27
申请号：US17161552
申请日：2021-01-28
Applicant: Silicon Motion, Inc.
Inventor： Fu-Jen Shih
Abstract: A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.
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公开(公告)号：US12124331B2
公开(公告)日：2024-10-22
申请号：US18215796
申请日：2023-06-28
Applicant: Silicon Motion, Inc.
Inventor： Fu-Jen Shih
CPC classification number: G06F11/1068 , G06F11/0772
Abstract: An interface circuit includes multiple signal processing devices and a monitor and calibration module. The monitor and calibration module includes multiple monitor circuits, multiple calibration circuits, a compensation accelerator and a processor. The monitor circuits monitor at least one of an amplitude, a frequency and jitter in at least one of a reception signal and a transmission signal to correspondingly generate a monitored result and monitor at least one of power supplying voltage and ground voltage to correspondingly generate a monitored result. The compensation accelerator collects the monitored results and generates a calibration control signal corresponding to each calibration circuit according to calibration commands. The processor generates the calibration commands based on the monitored results. The calibration circuits perform a corresponding calibration operation on the corresponding signal processing device in response to the calibration control signal to adjust a characteristic value of the signal processing device.
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公开(公告)号：US20240202060A1
公开(公告)日：2024-06-20
申请号：US18219714
申请日：2023-07-10
Applicant: Silicon Motion, Inc.
Inventor： Fu-Jen Shih
CPC classification number: G06F11/0772 , G06F11/1441
Abstract: A data storage device includes an interface circuit to process reception signals received from a peer device and transmission signals to be transmitted to the peer device. The interface circuit includes at least one signal processing circuit to perform an error recovery procedure when an error has occurred in the data storage device. When performing the error recovery procedure, the signal processing circuit performs an operation of periodic line reset to repeatedly transmit a line reset signal to the peer device within a predetermined period until the predetermined period expires or another line reset signal representing an acknowledgment of the line reset signal has been received from the peer device.
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Patent Agency Ranking
公开(公告)号：US11747987B2
公开(公告)日：2023-09-05
申请号：US15868574
申请日：2018-01-11
Applicant: Silicon Motion, Inc.
Inventor： Fu-Jen Shih , Chia-Ching Huang
CPC classification number: G06F3/0613 , G06F3/0625 , G06F3/0659 , G06F3/0673 , G06F3/0679 , G06F13/4068 , G06F13/4295 , Y02D10/00
Abstract: An electronic device includes a data storage device and a host device. The host device is coupled to the data storage device via a predetermined interface and includes a processor. The processor dynamically adjusts a data transfer speed of the predetermined interface according to a data processing speed required by data to be read from or written to the data storage device.
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公开(公告)号：US11349692B2
公开(公告)日：2022-05-31
申请号：US17346755
申请日：2021-06-14
Applicant: Silicon Motion, Inc.
Inventor： Fu-Jen Shih
Abstract: The invention introduces a non-transitory computer program product for adjusting equalization when executed by a processing unit of a storage device. The non-transitory computer program product includes program code to: activate an eye-diagram analyzer to adjust a parameter of an equalizer according to magnitudes corresponding to an eye-diagram, which are generated by the eye-diagram analyzer, and repeatedly adjust a parameter of the equalizer after a symbol decoding error is detected until an adjustment failure is detected or successive waveforms output from the equalizer belong to an eye open state. The symbol decoding error is detected during a reception of host data from a host side according to a command issued by the host side, which is defined in Universal Flash Storage (UFS) specification.
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公开(公告)号：US12093131B2
公开(公告)日：2024-09-17
申请号：US18215181
申请日：2023-06-28
Applicant: Silicon Motion, Inc.
Inventor： Fu-Jen Shih
CPC classification number: G06F11/1068 , G06F11/076 , G06F11/3037
Abstract: An interface circuit includes a signal processing circuit including multiple signal processing devices and a monitor and calibration module. The monitor and calibration module includes multiple monitor circuits, a processor and a calibration circuit. The monitor circuits monitor at least one of an amplitude, a frequency and a jitter in at least one of a reception signal and a transmission signal to correspondingly generate a monitored result and monitor at least one of power supplying voltage and ground voltage to correspondingly generate a monitored result. The processor collects the monitored results and determines a calibration operation based on the monitored results. The calibration circuit is coupled to the processor and at least one signal processing device and performs the calibration operation on the signal processing device to adjust a characteristic value of the signal processing device.
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公开(公告)号：US20240202070A1
公开(公告)日：2024-06-20
申请号：US18219087
申请日：2023-07-06
Applicant: Silicon Motion, Inc.
Inventor： Fu-Jen Shih
CPC classification number: G06F11/1068 , G06F11/076
Abstract: A data storage device includes at least one signal processing circuit to perform an error recovery procedure when an error has occurred in the data storage device. When performing the error recovery procedure, the signal processing circuit determines which type of line reset is to be performed according to a device identifier. When the device identifier satisfies a predetermined condition, the signal processing circuit performs an operation of periodic line reset to repeatedly transmit a line reset signal to the peer device in a predetermined period until the predetermined period expires or another line reset signal representing an acknowledgment of the line reset signal is received from the peer device; and when the device identifier does not satisfy the predetermined condition, the signal processing circuit performs an operation of one-shot line reset to transmit the line reset signal to the peer device for only one time.
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公开(公告)号：US20230171005A1
公开(公告)日：2023-06-01
申请号：US17951090
申请日：2022-09-22
Applicant: Silicon Motion, Inc.
Inventor： Fu-Jen Shih
Abstract: A method, for calibrating signal processing devices in an interface circuit coupled to a host device, comprises: negotiating with the host device in a link up process about an operation mode for the interface circuit to operate in a calibration procedure; and calibrating a characteristic value of a first signal processing device and a characteristic value of a second signal processing device in the calibration procedure. The first signal processing device is disposed on a receiving signal processing path and configured to process a received signal and the second signal processing device is disposed on a transmitting signal processing path and configured to process a transmitting signal, and the interface circuit is configured to operate based on the operation mode in the calibration procedure.
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