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    Method of forming split gate memory cells with thinner tunnel oxide
    1.
    发明授权
    Method of forming split gate memory cells with thinner tunnel oxide 有权

    公开(公告)号：US11488970B2

    公开(公告)日：2022-11-01

    申请号：US17179057

    申请日：2021-02-18

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Jeng-Wei Yang ,  Man-Tang Wu ,  Boolean Fan ,  Nhan Do

    IPC: H01L27/11524 ,  G11C16/04 ,  H01L29/66

    Abstract: A method of forming a memory cell includes forming a first polysilicon block over an upper surface of a semiconductor substrate and having top surface and a side surface meeting at a sharp edge, forming an oxide layer with a first portion over the upper surface, a second portion directly on the side surface, and a third portion directly on the sharp edge, performing an etch that thins the oxide layer in a non-uniform manner such that the third portion is thinner than the first and second portions, performing an oxide deposition that thickens the first, second and third portions of the oxide layer, wherein after the oxide deposition, the third portion is thinner than the first and second portions, and forming a second polysilicon block having one portion directly on the first portion of the oxide layer and another portion directly on the third portion of the oxide layer.

    Split-gate flash memory array with byte erase operation
    2.
    发明授权
    Split-gate flash memory array with byte erase operation 有权

    公开(公告)号：US10607703B2

    公开(公告)日：2020-03-31

    申请号：US16042000

    申请日：2018-07-23

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hsuan Liang ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Nhan Do ,  Hieu Van Tran

    IPC: G11C16/16 ,  G11C16/04 ,  H01L27/11521

    Abstract: A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.

    Formation Of Self-Aligned Source For Split-Gate Non-volatile Memory Cell
    6.
    发明申请
    Formation Of Self-Aligned Source For Split-Gate Non-volatile Memory Cell 有权
    用于分离门非易失性存储器单元的自对准源的形成

    公开(公告)号：US20150008451A1

    公开(公告)日：2015-01-08

    申请号：US14319893

    申请日：2014-06-30

    Applicant: SILICON STORAGE TECHNOLOGY, INC.

    Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Yueh-Hsin Chen

    IPC: H01L27/115 ,  H01L21/8234

    CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/823425 ,  H01L29/1608 ,  H01L29/42328 ,  H01L29/66825

    Abstract: A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. A pair of first spacers of insulation material extending along control gate inner sidewalls and over the floating gates. The floating gate inner sidewalls are aligned with side surfaces of the first spacers. A pair of second spacers of insulation material each extend along one of the first spacers and along one of the floating gate inner sidewalls. A trench formed into the substrate having sidewalls aligned with side surfaces of the second spacers. Silicon carbon disposed in the trench. Material implanted into the silicon carbon forming a first region having a second conductivity type.

    Abstract translation: 一种具有一对导电浮动栅极的存储器件，所述导电浮动栅极具有彼此相对的内侧壁，并且设置在第一导电类型的衬底上并与其绝缘。 一对间隔开的导电控制栅极，每个导电控制栅极设置在浮动栅极中的一个上并与其绝缘，并且每个包括面向彼此的内侧壁。 一对绝缘材料的第一间隔物，沿着控制栅极内侧壁和浮动栅极延伸。 浮动门内侧壁与第一间隔件的侧表面对准。 绝缘材料的一对第二间隔物各自沿着第一间隔件中的一个并且沿着浮动栅极内侧壁中的一个延伸。 形成在衬底中的沟槽，其具有与第二间隔物的侧表面对齐的侧壁。 设置在沟槽中的硅碳。 材料注入到硅碳中，形成具有第二导电类型的第一区域。

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