公开(公告)号：US11488970B2

公开(公告)日：2022-11-01

申请号：US17179057

申请日：2021-02-18

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei Yang ,  Man-Tang Wu ,  Boolean Fan ,  Nhan Do

IPC: H01L27/11524 ,  G11C16/04 ,  H01L29/66

Abstract: A method of forming a memory cell includes forming a first polysilicon block over an upper surface of a semiconductor substrate and having top surface and a side surface meeting at a sharp edge, forming an oxide layer with a first portion over the upper surface, a second portion directly on the side surface, and a third portion directly on the sharp edge, performing an etch that thins the oxide layer in a non-uniform manner such that the third portion is thinner than the first and second portions, performing an oxide deposition that thickens the first, second and third portions of the oxide layer, wherein after the oxide deposition, the third portion is thinner than the first and second portions, and forming a second polysilicon block having one portion directly on the first portion of the oxide layer and another portion directly on the third portion of the oxide layer.

公开(公告)号：US10607703B2

公开(公告)日：2020-03-31

申请号：US16042000

申请日：2018-07-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hsuan Liang ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Nhan Do ,  Hieu Van Tran

IPC: G11C16/16 ,  G11C16/04 ,  H01L27/11521

Abstract: A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.

公开(公告)号：US20170345840A1

公开(公告)日：2017-11-30

申请号：US15489548

申请日：2017-04-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Hieu Van Tran ,  Nhan Do

IPC: H01L27/11568 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/8238

CPC classification number: H01L27/11568 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/823821 ,  H01L28/00

Abstract: A method of forming a memory device with memory cells over a planar substrate surface and FinFET logic devices over fin shaped substrate surface portions, including forming a protective layer over previously formed floating gates, erase gates, word line poly and source regions in a memory cell portion of the substrate, then forming fins into the surface of the substrate and forming logic gates along the fins in a logic portion of the substrate, then removing the protective layer and completing formation of word line gates from the word line poly and drain regions in the memory cell portion of the substrate.

公开(公告)号：US09887206B2

公开(公告)日：2018-02-06

申请号：US15453829

申请日：2017-03-08

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Hieu Van Tran ,  Nhan Do

IPC: H01L21/336 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/11551 ,  H01L29/0847 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/7881

Abstract: A non-volatile memory cell, and method of making, that includes a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.

公开(公告)号：US09721958B2

公开(公告)日：2017-08-01

申请号：US15003659

申请日：2016-01-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei Yang ,  Chun-Ming Chen ,  Man-Tang Wu ,  Feng Zhou ,  Xian Liu ,  Chien-Sheng Su ,  Nhan Do

IPC: H01L21/336 ,  H01L27/11524 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11536 ,  H01L21/306

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L21/30604 ,  H01L27/11536 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming a memory device by forming spaced apart first and second regions with a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, forming a control gate over and insulated from the floating gate, forming an erase gate over and insulated from the first region, and forming a select gate over and insulated from a second portion of the channel region. Forming of the floating gate includes forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer, and performing two separate etches to form first and second trenches through the first conductive layer. A sidewall of the first conductive layer at the first trench has a negative slope and a sidewall of the first conductive layer at the second trench is vertical.

公开(公告)号：US20170117285A1

公开(公告)日：2017-04-27

申请号：US15290960

申请日：2016-10-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Chun-Ming Chen ,  Man-Tang Wu ,  Jeng-Wei Yang ,  Chien-Sheng Su ,  Nhan Do

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788

Abstract: A method of forming a non-volatile memory cell includes forming spaced apart first and second regions in a substrate, defining a channel region there between. A floating gate is formed over a first portion of the channel region and over a portion of the first region, wherein the floating gate includes a sharp edge disposed over the first region. A tunnel oxide layer is formed around the sharp edge. An erase gate is formed over the first region, wherein the erase gate includes a notch facing the sharp edge, and wherein the notch is insulated from the sharp edge by the tunnel oxide layer. A word line gate is formed over a second portion of the channel region which is adjacent to the second region. The forming of the word line gate is performed after the forming of the tunnel oxide layer and the erase gate.

公开(公告)号：US20160043095A1

公开(公告)日：2016-02-11

申请号：US14790540

申请日：2015-07-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Chien-Sheng Su ,  Nhan Do

IPC: H01L27/115 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L21/823425 ,  H01L21/823475 ,  H01L29/401 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A non-volatile memory cell includes a semiconductor substrate of first conductivity type, first and second spaced-apart regions in the substrate of second conductivity type, with a channel region in the substrate therebetween. A floating gate has a first portion disposed vertically over a first portion of the channel region, and a second portion disposed vertically over the first region. The floating gate includes a sloping upper surface that terminates with one or more sharp edges. An erase gate is disposed vertically over the floating gate with the one or more sharp edges facing the erase gate. A control gate has a first portion disposed laterally adjacent to the floating gate, and vertically over the first region. A select gate has a first portion disposed vertically over a second portion of the channel region, and laterally adjacent to the floating gate.

Abstract translation: 非易失性存储单元包括在第二导电类型的衬底中的第一导电类型的第一和第二间隔开的区域的半导体衬底，以及衬底中的沟道区。 浮动栅极具有垂直设置在沟道区域的第一部分上的第一部分和垂直设置在第一区域上的第二部分。 浮动门包括倾斜的上表面，其以一个或多个尖锐边缘终止。 擦除栅极垂直设置在浮动栅极上，其中一个或多个尖锐边缘面向擦除栅极。 控制门具有横向邻近浮动栅极设置的第一部分，并且垂直地设置在第一区域上。 选择栅极具有垂直设置在沟道区域的第二部分上并且横向邻近浮置栅极的第一部分。

公开(公告)号：US10714634B2

公开(公告)日：2020-07-14

申请号：US16166342

申请日：2018-10-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Chien-Sheng Su ,  Nhan Do

IPC: H01L29/788 ,  H01L27/11521 ,  H01L29/49 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/11524 ,  H01L27/11534 ,  H01L21/28

Abstract: A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. Portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed relative to the upper surface portion of the substrate under the logic device. The memory cell includes a polysilicon floating gate disposed over a first portion of a channel region of the substrate, a polysilicon word line gate disposed over a second portion of the channel region, a polysilicon erase gate disposed over a source region of the substrate, and a metal control gate disposed over the floating gate and insulated from the floating gate by a composite insulation layer that includes a high-K dielectric. The logic device includes a metal gate disposed over the substrate. The high voltage device includes a polysilicon gate disposed over the substrate.

公开(公告)号：US09793280B2

公开(公告)日：2017-10-17

申请号：US15057590

申请日：2016-03-01

Applicant: Silicon Storage Technology, Inc.

Inventor： Chun-Ming Chen ,  Jeng-Wei Yang ,  Chien-Sheng Su ,  Man-Tang Wu ,  Nhan Do

IPC: H01L29/66 ,  H01L27/11531 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11534 ,  G11C16/04

CPC classification number: H01L27/11531 ,  G11C16/0425 ,  H01L21/28273 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/66825

Abstract: A memory device and method including a semiconductor substrate with memory and logic device areas. A plurality of memory cells are formed in the memory area, each including first source and drain regions with a first channel region therebetween, a floating gate disposed over a first portion of the first channel region, a control gate disposed over the floating gate, a select gate disposed over a second portion of the first channel region, and an erase gate disposed over the source region. A plurality of logic devices formed in the logic device area, each including second source and drain regions with a second channel region therebetween, and a logic gate disposed over the second channel region. The substrate upper surface is recessed lower in the memory area than in the logic device area, so that the taller memory cells have an upper height similar to that of the logic devices.

公开(公告)号：US20170179141A1

公开(公告)日：2017-06-22

申请号：US15453829

申请日：2017-03-08

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Hieu Van Tran ,  Nhan Do

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/08 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/11551 ,  H01L29/0847 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/7881

Abstract: A non-volatile memory cell, and method of making, that includes a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.