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    Split Gate Non-volatile Flash Memory Cell Having A Silicon-Metal Floating Gate And Method Of Making Same
    3.
    发明申请
    Split Gate Non-volatile Flash Memory Cell Having A Silicon-Metal Floating Gate And Method Of Making Same 有权
    具有硅金属浮栅的分流门非易失性闪存单元及其制作方法

    公开(公告)号：US20150035040A1

    公开(公告)日：2015-02-05

    申请号：US13958483

    申请日：2013-08-02

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Jong-Won Yoo ,  Alexander Kotov ,  Yuri Tkachev ,  Chien-Sheng Su

    IPC: H01L29/788 ,  H01L29/66

    CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883

    Abstract: A non-volatile memory cell includes a substrate of a first conductivity type with first and second spaced apart regions of a second conductivity type, forming a channel region therebetween. A select gate is insulated from and disposed over a first portion of the channel region which is adjacent to the first region. A floating gate is insulated from and disposed over a second portion of the channel region which is adjacent the second region. Metal material is formed in contact with the floating gate. A control gate is insulated from and disposed over the floating gate. An erase gate includes a first portion insulated from and disposed over the second region and is insulated from and disposed laterally adjacent to the floating gate, and a second portion insulated from and laterally adjacent to the control gate and partially extends over and vertically overlaps the floating gate.

    Abstract translation: 非易失性存储单元包括具有第一和第二间隔开的第二导电类型的第一导电类型的衬底，在它们之间形成沟道区。 选择栅极与与第一区域相邻的沟道区域的第一部分绝缘并布置在其上。 浮动栅极与邻近第二区域的沟道区域的第二部分绝缘并布置在其上。 金属材料形成为与浮动栅极接触。 控制栅极与浮动栅极绝缘并设置在浮动栅极上。 擦除栅极包括与第二区域绝缘并且布置在第二区域上的第一部分，并且与浮动栅极绝缘并横向邻近设置，以及与控制栅极绝缘并横向邻近控制栅极的第二部分，并且部分地延伸越过浮动 门。

    Method Of Programming A Split-Gate Flash Memory Cell With Erase Gate
    6.
    发明申请
    Method Of Programming A Split-Gate Flash Memory Cell With Erase Gate 审中-公开

    公开(公告)号：US20200066738A1

    公开(公告)日：2020-02-27

    申请号：US16209515

    申请日：2018-12-04

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Yuri Tkachev ,  Alexander Kotov ,  Nhan Do

    IPC: H01L27/11521 ,  H01L29/788 ,  G11C16/04

    Abstract: A memory device with a memory cell and control circuitry. The memory cell includes source and drain regions formed in a semiconductor substrate, with a channel region extending there between. A floating gate is disposed over a first portion of the channel region for controlling its conductivity. A select gate is disposed over a second portion of the channel region for controlling its conductivity. A control gate is disposed over the floating gate. An erase gate is disposed over the source region and adjacent to the floating gate. The control circuitry is configured to perform a program operation by applying a negative voltage to the erase gate for causing electrons to tunnel from the erase gate to the floating gate, and perform an erase operation by applying a positive voltage to the erase gate for causing electrons to tunnel from the floating gate to the erase gate.

    Method of operating a split gate flash memory cell with coupling gate
    8.
    发明授权
    Method of operating a split gate flash memory cell with coupling gate 有权
    操作具有耦合栅极的分离栅极闪存单元的方法

    公开(公告)号：US09245638B2

    公开(公告)日：2016-01-26

    申请号：US14216776

    申请日：2014-03-17

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do ,  Elizabeth A. Cuevas ,  Yuri Tkachev ,  Mandana Tadayoni ,  Henry A. Om'mani

    IPC: G11C16/04 ,  G11C16/26 ,  H01L27/115 ,  G11C16/14

    CPC classification number: G11C16/26 ,  G11C16/0433 ,  G11C16/14 ,  H01L27/115

    Abstract: A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the fir region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.

    Abstract translation: 一种操作存储单元的方法，所述存储单元包括在衬底中间隔开的沟道区域中的第一和第二区域，设置在所述沟道区域和所述冷杉区域上方的浮置栅极，设置在所述沟道区域上方且横向邻近 浮动栅极，其具有设置在浮置栅极上的部分，以及耦合栅极，设置在第一区域上并且横向邻近浮动栅极。 擦除存储单元的方法包括向控制栅极施加正电压，向耦合栅极施加负电压。 读取存储单元的方法包括向控制栅极，耦合栅极以及第一和第二区域之一施加正电压。

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