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公开(公告)号:US09668351B2
公开(公告)日:2017-05-30
申请号:US14686785
申请日:2015-04-15
Applicant: Subtron Technology Co., Ltd.
Inventor: Chao-Min Wang
IPC: H05K3/00 , H05K1/18 , H01L23/498 , H01L21/683 , H01L21/48
CPC classification number: H05K1/187 , B32B2439/00 , H01L21/4857 , H01L21/6835 , H01L23/49822 , H01L2221/68318 , H01L2221/68345 , H01L2221/68381 , H01L2924/0002 , H05K3/007 , H01L2924/00
Abstract: A manufacturing method of a package carrier is provided. A carrier having a connecting surface is provided. A releasable solder resist layer is formed on the connecting surface of the carrier and completely covers the connecting surface. A substrate having an upper surface and a lower surface opposite to each other is provided. A first patterned solder resist layer is formed on the lower surfaces of the substrate and exposes a portion of the lower surface. The carrier and the substrate are laminated, the releasable solder resist layer directly contacts the first patterned solder resist layer, and the carrier is temporarily bonded to the first patterned solder resist layer through the releasable solder resist layer.
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公开(公告)号:US09761515B2
公开(公告)日:2017-09-12
申请号:US15475133
申请日:2017-03-31
Applicant: Subtron Technology Co., Ltd.
Inventor: Chao-Min Wang
IPC: H01L23/498 , H01L23/13 , H01L21/48 , H01L21/683
CPC classification number: H01L23/49822 , H01L21/4857 , H01L21/6835 , H01L23/13 , H01L23/49838 , H01L23/49866 , H01L2221/68345 , H01L2221/68381 , H05K1/0296 , H05K1/0298 , H05K1/09 , H05K3/0058 , H05K3/0061 , H05K3/048 , H05K3/06 , H05K3/064 , H05K3/14 , H05K3/4652 , H05K3/4682 , H05K2201/0145 , H05K2203/0152 , H05K2203/0502 , H05K2203/0548 , H05K2203/066
Abstract: A substrate structure includes a dielectric layer, a metal foil, a patterned metal layer, a first patterned solder-resist layer, a release layer and a second patterned solder-resist layer. The dielectric layer includes a first surface having a plurality of recesses and a second surface. The metal foil is disposed on the second surface. The patterned metal layer is disposed on the first surface, the patterned metal layer has a plurality of openings, and the openings are respectively corresponding to and expose the recesses. The first patterned solder-resist layer is filled in each of the recesses and corresponding to each of the openings. A top surface of the first patterned solder-resist layer is substantially coplanar with a top surface of the patterned metal layer. The second patterned solder-resist layer is disposed on the first patterned solder-resist layer and in the openings, and covers a portion of the patterned metal layer.
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公开(公告)号:US20160204054A1
公开(公告)日:2016-07-14
申请号:US14686785
申请日:2015-04-15
Applicant: Subtron Technology Co., Ltd.
Inventor: Chao-Min Wang
IPC: H01L23/498 , H01L21/48 , H01L21/683 , B32B37/14 , B32B37/06
CPC classification number: H05K1/187 , B32B2439/00 , H01L21/4857 , H01L21/6835 , H01L23/49822 , H01L2221/68318 , H01L2221/68345 , H01L2221/68381 , H01L2924/0002 , H05K3/007 , H01L2924/00
Abstract: A manufacturing method of a package carrier is provided. A carrier having a connecting surface is provided. A releasable solder resist layer is formed on the connecting surface of the carrier and completely covers the connecting surface. A substrate having an upper surface and a lower surface opposite to each other is provided. A first patterned solder resist layer is formed on the lower surfaces of the substrate and exposes a portion of the lower surface. The carrier and the substrate are laminated, the releasable solder resist layer directly contacts the first patterned solder resist layer, and the carrier is temporarily bonded to the first patterned solder resist layer through the releasable solder resist layer.
Abstract translation: 提供了一种封装载体的制造方法。 提供具有连接表面的载体。 在载体的连接表面上形成可剥离的阻焊层,并且完全覆盖连接表面。 提供具有彼此相对的上表面和下表面的基板。 第一图案化阻焊层形成在基板的下表面上并暴露下表面的一部分。 载体和基板层叠,可剥离阻焊层直接接触第一图案化阻焊层,载体通过可剥离阻焊层临时接合到第一图案化阻焊层。
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公开(公告)号:US20170207156A1
公开(公告)日:2017-07-20
申请号:US15475133
申请日:2017-03-31
Applicant: Subtron Technology Co., Ltd.
Inventor: Chao-Min Wang
IPC: H01L23/498 , H01L21/48 , H01L21/683 , H01L23/13
CPC classification number: H01L23/49822 , H01L21/4857 , H01L21/6835 , H01L23/13 , H01L23/49838 , H01L23/49866 , H01L2221/68345 , H01L2221/68381 , H05K1/0296 , H05K1/0298 , H05K1/09 , H05K3/0058 , H05K3/0061 , H05K3/048 , H05K3/06 , H05K3/064 , H05K3/14 , H05K3/4652 , H05K3/4682 , H05K2201/0145 , H05K2203/0152 , H05K2203/0502 , H05K2203/0548 , H05K2203/066
Abstract: A substrate structure includes a dielectric layer, a metal foil, a patterned metal layer, a first patterned solder-resist layer, a release layer and a second patterned solder-resist layer. The dielectric layer includes a first surface having a plurality of recesses and a second surface. The metal foil is disposed on the second surface. The patterned metal layer is disposed on the first surface, the patterned metal layer has a plurality of openings, and the openings are respectively corresponding to and expose the recesses. The first patterned solder-resist layer is filled in each of the recesses and corresponding to each of the openings. A top surface of the first patterned solder-resist layer is substantially coplanar with a top surface of the patterned metal layer. The second patterned solder-resist layer is disposed on the first patterned solder-resist layer and in the openings, and covers a portion of the patterned metal layer.
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公开(公告)号:US09648760B2
公开(公告)日:2017-05-09
申请号:US15052885
申请日:2016-02-25
Applicant: Subtron Technology Co., Ltd.
Inventor: Chao-Min Wang
CPC classification number: H01L23/49822 , H01L21/4857 , H01L21/6835 , H01L23/13 , H01L23/49838 , H01L23/49866 , H01L2221/68345 , H01L2221/68381 , H05K1/0296 , H05K1/0298 , H05K1/09 , H05K3/0058 , H05K3/0061 , H05K3/048 , H05K3/06 , H05K3/064 , H05K3/14 , H05K3/4652 , H05K3/4682 , H05K2201/0145 , H05K2203/0152 , H05K2203/0502 , H05K2203/0548 , H05K2203/066
Abstract: A substrate structure includes a dielectric layer, a metal foil, a patterned metal layer, a first patterned solder-resist layer and a second patterned solder-resist layer. The dielectric layer includes a first surface and a second surface, and the first surface has a plurality of recesses. The metal foil is disposed on the second surface. The patterned metal layer is disposed on the first surface, the patterned metal layer has a plurality of openings, and the openings are respectively corresponding to and expose the recesses. The first patterned solder-resist layer is filled in each of the recesses and corresponding to each of the openings. A top surface of the first patterned solder-resist layer is substantially coplanar with a top surface of the patterned metal layer. The second patterned solder-resist layer is disposed on the first patterned solder-resist layer and in the openings, and covers a portion of the patterned metal layer.
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公开(公告)号:US20160174390A1
公开(公告)日:2016-06-16
申请号:US15052885
申请日:2016-02-25
Applicant: Subtron Technology Co., Ltd.
Inventor: Chao-Min Wang
CPC classification number: H01L23/49822 , H01L21/4857 , H01L21/6835 , H01L23/13 , H01L23/49838 , H01L23/49866 , H01L2221/68345 , H01L2221/68381 , H05K1/0296 , H05K1/0298 , H05K1/09 , H05K3/0058 , H05K3/0061 , H05K3/048 , H05K3/06 , H05K3/064 , H05K3/14 , H05K3/4652 , H05K3/4682 , H05K2201/0145 , H05K2203/0152 , H05K2203/0502 , H05K2203/0548 , H05K2203/066
Abstract: A substrate structure includes a dielectric layer, a metal foil, a patterned metal layer, a first patterned solder-resist layer and a second patterned solder-resist layer. The dielectric layer includes a first surface and a second surface, and the first surface has a plurality of recesses. The metal foil is disposed on the second surface. The patterned metal layer is disposed on the first surface, the patterned metal layer has a plurality of openings, and the openings are respectively corresponding to and expose the recesses. The first patterned solder-resist layer is filled in each of the recesses and corresponding to each of the openings. A top surface of the first patterned solder-resist layer is substantially coplanar with a top surface of the patterned metal layer. The second patterned solder-resist layer is disposed on the first patterned solder-resist layer and in the openings, and covers a portion of the patterned metal layer.
Abstract translation: 基板结构包括电介质层,金属箔,图案化金属层,第一图案化阻焊层和第二图案化阻焊层。 电介质层包括第一表面和第二表面,并且第一表面具有多个凹部。 金属箔设置在第二表面上。 图案化金属层设置在第一表面上,图案化金属层具有多个开口,并且开口分别对应于并露出凹部。 第一图案化阻焊层填充在每个凹部中并对应于每个开口。 第一图案化阻焊层的顶表面与图案化金属层的顶表面基本共面。 第二图案化阻焊层设置在第一图案化阻焊层和开口中,并且覆盖图案化金属层的一部分。
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