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公开(公告)号：US20160230286A1
公开(公告)日：2016-08-11
申请号：US14685610
申请日：2015-04-14
Applicant: Subtron Technology Co., Ltd.
Inventor： Chin-Sheng Wang , Chien-Ming Chen
CPC classification number: B65D65/40 , B32B37/02 , B32B37/12 , B32B38/06 , B32B2038/047 , B32B2311/12 , B32B2457/08 , C25D5/022 , C25D5/12 , C25D7/00 , H01L25/0655 , H01L2224/0401 , H01L2224/04042 , H01L2224/11462 , H01L2924/15313
Abstract: A manufacturing method of a package substrate is provided. A first base is formed. Metal bumps are formed on the first base by plating. A second base having an upper and a lower surfaces, a core dielectric layer, a first and a second copper foil layers and containing cavities is provided. An adhesive layer is formed on inner walls of the containing cavities. The first and the second bases are laminated so that the metal bumps are disposed inside the containing cavities. A first base is removed. Blind via holes extending from the upper surface to the metal bumps are formed. A conductive material layer is formed on the first and the second copper foil layers, wherein the conductive material layer fills the blind via holes so as to define conductive through via holes. The conductive material layer is patterned to form a first and a second patterned metal layers.
Abstract translation: 提供封装基板的制造方法。 形成第一个基座。 通过电镀在第一基体上形成金属凸块。 提供具有上表面和下表面的第二基底，芯介质层，第一和第二铜箔层和容纳腔。 在容纳腔的内壁上形成粘合剂层。 层叠第一和第二基底，使得金属凸块设置在容纳腔内。 第一个基地被删除。 形成从上表面延伸到金属凸块的盲孔。 导电材料层形成在第一和第二铜箔层上，其中导电材料层填充盲孔，以便通过通孔限定导电。 图案化导电材料层以形成第一和第二图案化金属层。
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公开(公告)号：US10319610B2
公开(公告)日：2019-06-11
申请号：US15828334
申请日：2017-11-30
Applicant: Subtron Technology Co., Ltd.
Inventor： Chin-Sheng Wang , Shih-Hao Sun
IPC: H01L21/56 , H01L21/683 , H01L21/48 , H01L23/498 , H01L23/13 , H01L23/367 , H01L23/373 , H01L23/31
Abstract: A package carrier includes a substrate, at least one heat conducting element, an insulating material, a first patterned circuit layer and a second patterned circuit layer. The substrate has an upper surface, a lower surface and a through hole. The heat conducting element is disposed inside the through hole and has a first surface and a second surface. The insulating material has a top surface, a bottom surface and at least one cavity extending from the top surface to the heat conducting element. The heat conducting element is fixed in the through hole by the insulating material, and the cavity exposes a portion of the first surface of the heat conducting element. The first patterned circuit layer is disposed on the upper surface and the top surface, and the second patterned circuit layer is disposed on the lower surface and the bottom surface.
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公开(公告)号：US20170325330A1
公开(公告)日：2017-11-09
申请号：US15176130
申请日：2016-06-07
Applicant: Subtron Technology Co., Ltd.
Inventor： Chin-Sheng Wang , Ching-Sheng Chen , Ching-Ta Chen , Mei-Chin Chang
Abstract: A manufacturing method of a circuit substrate includes the following steps. A core layer having a core dielectric layer, a first patterned circuit layer and a second patterned circuit layer is provided. An electroless plating nickel layer is formed on the first patterned circuit layer and the second patterned circuit layer. The electroless plating nickel layer has a first thickness, and the first thickness is between 1 micrometer and 10 micrometers. A reducing process is performed on the electroless plating nickel layer so that the electroless plating nickel layer is thinned from the first thickness to a second thickness to form a thinned electroless plating nickel layer. The second thickness is between 0.01 micrometers and 0.9 micrometers. An electroless plating palladium layer is formed on the thinned electroless plating nickel layer. A surface metal passivation layer is formed on the electroless plating palladium layer.
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公开(公告)号：US09458540B2
公开(公告)日：2016-10-04
申请号：US14685610
申请日：2015-04-14
Applicant: Subtron Technology Co., Ltd.
Inventor： Chin-Sheng Wang , Chien-Ming Chen
CPC classification number: B65D65/40 , B32B37/02 , B32B37/12 , B32B38/06 , B32B2038/047 , B32B2311/12 , B32B2457/08 , C25D5/022 , C25D5/12 , C25D7/00 , H01L25/0655 , H01L2224/0401 , H01L2224/04042 , H01L2224/11462 , H01L2924/15313
Abstract: A manufacturing method of a package substrate is provided. A first base is formed. Metal bumps are formed on the first base by plating. A second base having an upper and a lower surfaces, a core dielectric layer, a first and a second copper foil layers and containing cavities is provided. An adhesive layer is formed on inner walls of the containing cavities. The first and the second bases are laminated so that the metal bumps are disposed inside the containing cavities. A first base is removed. Blind via holes extending from the upper surface to the metal bumps are formed. A conductive material layer is formed on the first and the second copper foil layers, wherein the conductive material layer fills the blind via holes so as to define conductive through via holes. The conductive material layer is patterned to form a first and a second patterned metal layers.
Abstract translation: 提供封装基板的制造方法。 形成第一个基座。 通过电镀在第一基体上形成金属凸块。 提供具有上表面和下表面的第二基底，芯介质层，第一和第二铜箔层和容纳腔。 在容纳腔的内壁上形成粘合剂层。 层叠第一和第二基底，使得金属凸块设置在容纳腔内。 第一个基地被删除。 形成从上表面延伸到金属凸块的盲孔。 导电材料层形成在第一和第二铜箔层上，其中导电材料层填充盲孔，以便通过通孔限定导电。 图案化导电材料层以形成第一和第二图案化金属层。
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公开(公告)号：US10177067B2
公开(公告)日：2019-01-08
申请号：US15598324
申请日：2017-05-18
Applicant: Subtron Technology Co., Ltd.
Inventor： Chin-Sheng Wang , Chih-Hsien Cheng , Shih-Hao Sun
IPC: H01L21/48 , H01L23/00 , H01L23/367 , H01L23/498
Abstract: A manufacturing method including following steps is provided. A substrate that includes a core layer, a first conductive layer, and a second conductive layer is provided. A heat conducting channel is formed in the substrate, and an adhesion layer is formed on the second conductive layer to cover a side of the heat conducting channel. A heat conducting element and a buffer layer are placed into the heat conducting channel, and a gap is formed between either the heat conducting element or the buffer layer and an inner side surface of the heat conducting channel. The gap is filled with a first insulant material, and the adhesion layer and the buffer layer are removed to form a cavity and expose the heat conducting element. The first conductive layer and the second conductive layer are patterned to form a first patterned circuit layer and a second patterned circuit layer, respectively.
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Patent Agency Ranking
公开(公告)号：US20180090339A1
公开(公告)日：2018-03-29
申请号：US15828334
申请日：2017-11-30
Applicant: Subtron Technology Co., Ltd.
Inventor： Chin-Sheng Wang , Shih-Hao Sun
IPC: H01L21/56 , H01L23/13 , H01L23/367 , H01L23/373 , H01L23/498 , H01L21/48 , H01L21/683
CPC classification number: H01L21/56 , H01L21/4857 , H01L21/6835 , H01L23/13 , H01L23/3121 , H01L23/3677 , H01L23/373 , H01L23/3731 , H01L23/3738 , H01L23/49822 , H01L23/49838 , H01L2221/68359 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15153 , H01L2924/1531 , Y10T29/4913 , H01L2924/00014 , H01L2924/00
Abstract: A package carrier includes a substrate, at least one heat conducting element, an insulating material, a first patterned circuit layer and a second patterned circuit layer. The substrate has an upper surface, a lower surface and a through hole. The heat conducting element is disposed inside the through hole and has a first surface and a second surface. The insulating material has a top surface, a bottom surface and at least one cavity extending from the top surface to the heat conducting element. The heat conducting element is fixed in the through hole by the insulating material, and the cavity exposes a portion of the first surface of the heat conducting element. The first patterned circuit layer is disposed on the upper surface and the top surface, and the second patterned circuit layer is disposed on the lower surface and the bottom surface.
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公开(公告)号：US09870931B2
公开(公告)日：2018-01-16
申请号：US15000034
申请日：2016-01-19
Applicant: Subtron Technology Co., Ltd.
Inventor： Chin-Sheng Wang , Shih-Hao Sun
IPC: H05K3/30 , H01L21/56 , H01L21/683 , H01L21/48 , H01L23/498 , H01L23/13 , H01L23/367 , H01L23/373 , H01L23/31
CPC classification number: H01L21/56 , H01L21/4857 , H01L21/6835 , H01L23/13 , H01L23/3121 , H01L23/3677 , H01L23/373 , H01L23/3731 , H01L23/3738 , H01L23/49822 , H01L23/49838 , H01L2221/68359 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15153 , H01L2924/1531 , Y10T29/4913 , H01L2924/00014 , H01L2924/00
Abstract: A package carrier includes a substrate, at least one heat conducting element, an insulating material, a first patterned circuit layer and a second patterned circuit layer. The substrate has an upper surface, a lower surface and a through hole. The heat conducting element is disposed inside the through hole and has a first surface and a second surface. The insulating material has a top surface, a bottom surface and at least one cavity extending from the top surface to the heat conducting element. The heat conducting element is fixed in the through hole by the insulating material, and the cavity exposes a portion of the first surface of the heat conducting element. The first patterned circuit layer is disposed on the upper surface and the top surface, and the second patterned circuit layer is disposed on the lower surface and the bottom surface.
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公开(公告)号：US09591753B2
公开(公告)日：2017-03-07
申请号：US14849614
申请日：2015-09-10
Applicant: Subtron Technology Co., Ltd.
Inventor： Chin-Sheng Wang , Ching-Sheng Chen , Mei-Chin Chang , Ching-Ta Chen
CPC classification number: H05K1/09 , H05K1/111 , H05K3/181 , H05K3/188 , H05K3/244 , H05K2201/0338 , H05K2201/0344 , H05K2201/09472 , H05K2201/099 , H05K2203/072
Abstract: A circuit board includes a substrate, a patterned copper layer, a phosphorous-containing electroless plating palladium layer, an electroless plating palladium layer and an immersion plating gold layer. The patterned copper layer is disposed on the substrate. The phosphorous-containing electroless plating palladium layer is disposed on the patterned copper layer, wherein in the phosphorous-containing electroless plating palladium layer, a weight percentage of phosphorous is in a range from 4% to 6%, and a weight percentage of palladium is in a range from 94% to 96%. The electroless plating palladium layer is disposed on the phosphorous-containing electroless plating palladium layer, wherein in the electroless plating palladium layer, a weight percentage of palladium is 99% or more. The immersion plating gold layer is disposed on the electroless plating palladium layer.
Abstract translation: 电路板包括基板，图案化铜层，含磷化学镀钯层，无电镀钯层和浸镀金层。 图案化铜层设置在基板上。 含磷化学镀钯层设置在图案化的铜层上，其中，在含磷化学镀钯层中，磷的重量百分比为4〜6％，钯的重量百分比为 在94％至96％的范围内。 无电镀钯层配置在含磷化学镀钯层上，其中，在化学镀钯层中，钯的重量百分比为99％以上。 浸镀金层设置在化学镀钯层上。
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公开(公告)号：US20180114739A1
公开(公告)日：2018-04-26
申请号：US15598324
申请日：2017-05-18
Applicant: Subtron Technology Co., Ltd.
Inventor： Chin-Sheng Wang , Chih-Hsien Cheng , Shih-Hao Sun
IPC: H01L23/367 , H01L21/48 , H01L23/498 , H01L23/00
CPC classification number: H01L23/3675 , H01L21/4857 , H01L21/486 , H01L21/4882 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/49866 , H01L24/49 , H01L2224/48091 , H01L2924/15153 , H01L2924/00014
Abstract: A manufacturing method including following steps is provided. A substrate that includes a core layer, a first conductive layer, and a second conductive layer is provided. A heat conducting channel is formed in the substrate, and an adhesion layer is formed on the second conductive layer to cover a side of the heat conducting channel. A heat conducting element and a buffer layer are placed into the heat conducting channel, and a gap is formed between either the heat conducting element or the buffer layer and an inner side surface of the heat conducting channel. The gap is filled with a first insulant material, and the adhesion layer and the buffer layer are removed to form a cavity and expose the heat conducting element. The first conductive layer and the second conductive layer are patterned to form a first patterned circuit layer and a second patterned circuit layer, respectively.
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公开(公告)号：US20170079128A1
公开(公告)日：2017-03-16
申请号：US15000034
申请日：2016-01-19
Applicant: Subtron Technology Co., Ltd.
Inventor： Chin-Sheng Wang , Shih-Hao Sun
IPC: H05K1/02 , H01L21/48 , H01L23/498 , H01L23/48 , H05K3/28 , H05K1/18 , H05K1/11 , H05K3/46 , H05K3/30 , H01L21/683 , H01L21/56
CPC classification number: H01L21/56 , H01L21/4857 , H01L21/6835 , H01L23/13 , H01L23/3121 , H01L23/3677 , H01L23/373 , H01L23/3731 , H01L23/3738 , H01L23/49822 , H01L23/49838 , H01L2221/68359 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15153 , H01L2924/1531 , Y10T29/4913 , H01L2924/00014 , H01L2924/00
Abstract: A package carrier includes a substrate, at least one heat conducting element, an insulating material, a first patterned circuit layer and a second patterned circuit layer. The substrate has an upper surface, a lower surface and a through hole. The heat conducting element is disposed inside the through hole and has a first surface and a second surface. The insulating material has a top surface, a bottom surface and at least one cavity extending from the top surface to the heat conducting element. The heat conducting element is fixed in the through hole by the insulating material, and the cavity exposes a portion of the first surface of the heat conducting element. The first patterned circuit layer is disposed on the upper surface and the top surface, and the second patterned circuit layer is disposed on the lower surface and the bottom surface.
Abstract translation: 封装载体包括衬底，至少一个导热元件，绝缘材料，第一图案化电路层和第二图案化电路层。 基板具有上表面，下表面和通孔。 导热元件设置在通孔的内部并具有第一表面和第二表面。 绝缘材料具有顶表面，底表面和从顶表面延伸到导热元件的至少一个腔。 导热元件通过绝缘材料固定在通孔中，并且空腔暴露导热元件的第一表面的一部分。 第一图案化电路层设置在上表面和顶表面上，第二图案化电路层设置在下表面和底表面上。
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