公开(公告)号：US10068936B2

公开(公告)日：2018-09-04

申请号：US14941747

申请日：2015-11-16

Applicant: SunASIC Technologies, Inc.

Inventor： Chung Hao Hsieh ,  Chi Chou Lin ,  Zheng Ping He

IPC: H01L27/146 ,  H05K1/18 ,  H05K3/30 ,  H01L31/0203 ,  G06K9/00 ,  H01L23/14 ,  H01L23/13

Abstract: A Printed Circuit Board Assembly (PCBA) for forming an enhanced biometric module and a method for manufacturing the PCBA are disclosed. The method includes the steps of providing a PCB, a biometric sensing chip and SMDs; mounting the biometric sensing chip on the PCB with each bonding pad being electrically linked to one corresponding first contact pad; mounting the SMDs on second contact pads which are electrically linked thereto, respectively; and forming a protection layer. The present invention takes advantages of compact size of small conductive elements to avoid cracks in the protection layer.

公开(公告)号：US10963546B2

公开(公告)日：2021-03-30

申请号：US15947956

申请日：2018-04-09

Applicant: SunASIC Technologies, Inc.

Inventor： Chi Chou Lin ,  Zheng Ping He

IPC: G06F21/32 ,  G06F21/62 ,  G06F16/23 ,  G07C9/37

Abstract: A biometric security device for digital key storing is disclosed. The biometric security device includes a biometric information fetching module and a processing module. The processing module has a nonvolatile storage unit and a processing unit. The nonvolatile storage unit includes a secure storage unit and a general storage unit. The biometric security device with a secure electronic key designed for storing secret data utilizes both TrustZone™ technology (or similar technology) and biometric authentication. Thus, it can provide the flexibility for multiple users or applications to use the biometric security device or any equipment the biometric security device mounted in without compromising the safeguard of the data stored therein.

公开(公告)号：US10452565B2

公开(公告)日：2019-10-22

申请号：US15869394

申请日：2018-01-12

Applicant: SunASIC Technologies, Inc.

Inventor： Chi Chou Lin ,  Hao-Jyh Liu ,  Zheng Ping He

IPC: G06F12/14 ,  G06Q50/18 ,  G06F21/10 ,  G06F21/57

Abstract: A secure electronic device is disclosed. The secure electronic device includes a first core processing unit, a secure boot Read-Only Memory, a first non-volatile memory, a first volatile memory and a first communication interface. A new framework based on the secure electronic device with built-in security is able to safeguard intellectual property for the developers and further improves the security of the secure electronic device. Thus, more developers can launch their programs or services without being stolen or tampered by an unauthorized party.

公开(公告)号：US10162995B2

公开(公告)日：2018-12-25

申请号：US15488536

申请日：2017-04-17

Applicant: SunASIC Technologies, Inc.

Inventor： Chi Chou Lin ,  Zheng Ping He

IPC: G06K9/00

Abstract: A capacitive image sensor with noise reduction feature and a method operating the capacitive image sensor are provided. The capacitive image sensor includes: a number of capacitive sensing units forming an array, each capacitive sensing unit for transforming a distance between a portion of a surface of an approaching finger and a top surface thereof into an output electric potential, wherein a value of the output electric potential is changed by a driving signal coupled on the finger; at least one sample-and-hold circuit for capturing and retaining different output electric potentials; at least one signal conditioning circuit, each comprising: at least one differential amplifier for amplifying a difference between two electric potentials retained by the sample-and-hold circuit; and a driving source, for providing the driving signal to the finger.

公开(公告)号：US10078776B2

公开(公告)日：2018-09-18

申请号：US15381182

申请日：2016-12-16

Applicant: SunASIC Technologies, Inc.

Inventor： Chi Chou Lin ,  Zheng Ping He

IPC: G06K9/00 ,  H04N5/365 ,  H03K17/96 ,  H01L27/06

CPC classification number: G06K9/0002 ,  H01L27/0629 ,  H03K17/9622 ,  H04N5/365

Abstract: A capacitive fingerprint sensor which includes capacitive sensing units is disclosed. Each of the capacitive sensing unit includes a sensing electrode; a first switch; a voltage follower; and a reference capacitor. The voltage follower includes an adjustable current source, for providing at least two distinct current levels; and a MOS transistor. The MOS transistor includes a source node, connected to ground via the adjustable current source and serves as an output node of the voltage follower; a gate node, connected to the sensing electrode and serves as an input node of the voltage follower; a drain node, connected to a power source, for providing power to the voltage follower; and a bulk node, connected to the source node.

公开(公告)号：US10037954B2

公开(公告)日：2018-07-31

申请号：US15460482

申请日：2017-03-16

Applicant: SunASIC Technologies, Inc.

Inventor： Chi Chou Lin ,  Zheng Ping He

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/78 ,  H01L23/544 ,  G06K9/00

CPC classification number: H01L24/06 ,  G06F3/044 ,  G06K9/00006 ,  G06K9/00013 ,  G06K9/0004 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L2223/5446 ,  H01L2224/03614 ,  H01L2224/05026 ,  H01L2224/06135 ,  H01L2224/0912

Abstract: A chip with I/O pads on the peripheries and a method making the chip is disclosed. The chip includes: a substrate; a first metal layer, formed above the substrate; an inter-metal dielectric layer, formed above the first metal layer, having concave portions formed along the peripheries of the chip so that a portion of the first metal layer is exposed to form an input-output (I/O) pad in each of the concave portions which are spaced apart from each other; and a passivation layer, formed above the second metal layer without covering the concave portions so that specific circuits are formed by the first metal layer and the second metal layer, respectively. By changing the I/O pad from the top of the chip to the peripheries, the extra thickness of the packaged chip caused by wire bonding in the prior arts can be reduced.