公开(公告)号：US11817534B1

公开(公告)日：2023-11-14

申请号：US17856958

申请日：2022-07-02

Applicant: TactoTek Oy

Inventor： Antti Keränen ,  Sami Torvinen ,  Tero Heikkinen ,  Pasi Korhonen ,  Pälvi Apilo ,  Mikko Heikkinen ,  Jarmo Sääski ,  Paavo Niskala ,  Ville Wallenius ,  Heikki Tuovinen ,  Janne Asikkala ,  Taneli Salmi ,  Suvi Kela ,  Outi Rusanen ,  Johanna Juvani ,  Mikko Sippari ,  Tomi Simula ,  Tapio Rautio ,  Samuli Yrjänä ,  Tero Rajaniemi ,  Simo Koivikko ,  Juha-Matti Hintikka ,  Hasse Sinivaara ,  Vinski Bräysy ,  Olimpia Migliore ,  Juha Sepponen

IPC: H01L33/60 ,  H01L33/62 ,  H01L25/075 ,  H01L33/00

CPC classification number: H01L33/60 ,  H01L25/0753 ,  H01L33/005 ,  H01L33/62 ,  H01L2933/0058 ,  H01L2933/0066

Abstract: An integrated optically functional multilayer structure includes a flexible, substrate film arranged with a circuit design including at least a number of electrical conductors preferably additively printed on the substrate film; a light source provided upon a first side of the substrate film to internally illuminate at least portion of the structure for external perception; an optically transmissive plastic layer produced upon the first side of the substrate film, said plastic layer at least laterally surrounding, the light source, the substrate film at least having a similar or lower refractive index therewith; and a reflector design comprising at least one material layer, said reflector design being configured to reflect, the light emitted by the light source and incident upon the reflector design.

公开(公告)号：US12096562B2

公开(公告)日：2024-09-17

申请号：US18644647

申请日：2024-04-24

Applicant: TactoTek Oy

Inventor： Mikko Heikkinen ,  Jarmo Sääski ,  Ilpo Hänninen ,  Antti Keränen ,  Tomi Simula ,  Vinski Bräysy ,  Pälvi Apilo ,  Pasi Korhonen ,  Topi Wuori

IPC: H05K1/02 ,  B29C51/14 ,  G01P1/02 ,  H05K1/18 ,  H05K3/00 ,  H05K3/14 ,  H05K3/30 ,  B29L31/34

CPC classification number: H05K1/185 ,  B29C51/14 ,  G01P1/02 ,  H05K3/0014 ,  H05K3/306 ,  B29L2031/3425 ,  H05K2201/10151 ,  H05K2201/10265 ,  H05K2203/1327 ,  H05K2203/166

Abstract: An interface assembly includes a functional multilayer structure that includes a first substrate a molded material layer on a first side of the first substrate, and a sensor arrangement including at least one sensor, wherein the sensor arrangement is arranged at least partly embedded into the molded material layer. The assembly further includes a movable member being movable relative to the functional multilayer structure, wherein the movable member includes at least one detection portion, and the sensor arrangement and the at least one detection portion are mutually arranged so that a position or a change of position of the movable member is detectable by the sensor arrangement based on a position or a change of position of the at least one detection portion relative to the sensor arrangement.

公开(公告)号：US12052829B2

公开(公告)日：2024-07-30

申请号：US18191427

申请日：2023-03-28

Applicant: TactoTek Oy

Inventor： Tomi Simula ,  Tapio Rautio

IPC: H05K1/02 ,  H01L23/24 ,  H01L23/36 ,  H01L23/492 ,  H01L23/58 ,  H05K1/03 ,  H05K1/11 ,  H05K3/00 ,  H05K3/12 ,  H05K3/28

CPC classification number: H05K3/284 ,  H05K1/0393 ,  H05K1/111 ,  H05K3/0067 ,  H05K3/1283 ,  H05K2203/1316 ,  H05K2203/1322

Abstract: The method for manufacturing a number of electrical nodes, wherein the method includes providing a number of electronic circuits onto a first substrate, such as on a printed circuit board or other electronics substrate, optionally, a low-temperature co-fired ceramic substrate, wherein each one of the electronic circuits includes a circuit pattern and at least one electronics component in connection with the circuit pattern, wherein the electronic circuits are spaced from each other on the first substrate, thereby defining a blank area surrounding each one of the number of electronic circuits, respectively, and providing potting or casting material to embed each one of the number of electronic circuits in the potting or casting material, and, subsequently, hardening, optionally including curing, the potting or casting material to form a filler material layer of the number of electrical nodes.

公开(公告)号：US11914184B2

公开(公告)日：2024-02-27

申请号：US18339467

申请日：2023-06-22

Applicant: TactoTek Oy

Inventor： Antti Keränen ,  Tero Heikkinen ,  Pasi Korhonen ,  Pälvi Apilo ,  Mikko Heikkinen ,  Jarmo Sääski ,  Paavo Niskala ,  Ville Wallenius ,  Heikki Tuovinen ,  Janne Asikkala ,  Taneli Salmi ,  Suvi Kela ,  Outi Rusanen ,  Johanna Juvani ,  Mikko Sippari ,  Tomi Simula ,  Tapio Rautio ,  Samuli Yrjänä ,  Tero Rajaniemi ,  Simo Koivikko ,  Juha-Matti Hintikka ,  Hasse Sinivaara ,  Vinski Bräysy ,  Olimpia Migliore ,  Juha Sepponen

IPC: F21V8/00 ,  G02B5/08

CPC classification number: G02B6/0031 ,  G02B6/004 ,  G02B6/0021 ,  G02B6/0036 ,  G02B6/0041 ,  G02B6/0043 ,  G02B6/0051 ,  G02B6/0055 ,  G02B6/0061 ,  G02B6/0065 ,  G02B6/0068 ,  G02B6/0073 ,  G02B6/0083 ,  G02B5/0883

Abstract: An integrated optically functional multilayer structure includes a flexible, substrate film arranged with a circuit design including at least a number of electrical conductors on the substrate film; and a plurality of top-emitting, bottom-installed light sources provided upon a first side of the substrate film to internally illuminate at least portion of the structure for external perception via associated outcoupling areas, wherein for each light source of the plurality of light sources there is optically transmissive plastic layer, produced upon the first side of the substrate film, said plastic layer at least laterally surrounding the light source, the substrate film at least having a similar or lower refractive index therewith; and reflector design including at least one material layer, provided at least upon the light source and configured to reflect the light emitted by the light source and incident upon the reflective layer towards the plastic layer.

公开(公告)号：US11729915B1

公开(公告)日：2023-08-15

申请号：US17700657

申请日：2022-03-22

Applicant: TactoTek Oy

Inventor： Tomi Simula ,  Tapio Rautio

IPC: H05K1/02 ,  H05K1/14 ,  H05K1/18 ,  H05K3/00 ,  H05K3/22 ,  H05K3/28 ,  H05K3/34 ,  H05K3/46 ,  H01L21/00 ,  H01L21/02 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L21/60 ,  H01L21/66 ,  H01L21/78 ,  H01L21/673 ,  H01L23/00 ,  H01L23/02 ,  H01L23/04 ,  H01L23/28 ,  H01L23/48 ,  H01L23/49 ,  H01L23/52 ,  H01L23/488 ,  H01L23/495 ,  H01L23/498 ,  H01L23/552 ,  H05K1/03 ,  H05K1/11 ,  H05K3/12

CPC classification number: H05K3/284 ,  H05K1/0393 ,  H05K1/111 ,  H05K3/0067 ,  H05K3/1283 ,  H05K2203/1316 ,  H05K2203/1322

Abstract: The method for manufacturing a number of electrical nodes, wherein the method includes providing a number of electronic circuits onto a first substrate, such as on a printed circuit board or other electronics substrate, optionally, a low-temperature co-fired ceramic substrate, wherein each one of the electronic circuits includes a circuit pattern and at least one electronics component in connection with the circuit pattern, wherein the electronic circuits are spaced from each other on the first substrate, thereby defining a blank area surrounding each one of the number of electronic circuits, respectively, and providing potting or casting material to embed each one of the number of electronic circuits in the potting or casting material, and, subsequently, hardening, optionally including curing, the potting or casting material to form a filler material layer of the number of electrical nodes.

公开(公告)号：US11357111B2

公开(公告)日：2022-06-07

申请号：US16113388

申请日：2018-08-27

Applicant: TactoTek Oy

Inventor： Janne Asikkala ,  Tomi Simula ,  Antti Keränen

IPC: H05K3/46 ,  H01L23/485 ,  H01L23/498 ,  H05K1/18 ,  H05K3/00 ,  H05K3/12 ,  H05K3/10 ,  H01R13/405 ,  H05K1/02

Abstract: A method for manufacturing an integrated multilayer structure includes obtaining a substrate film having first and second sides, providing at least on the first side one or more first functional features, arranging at least one layer upon at least the first side; removing, at least a portion of the substrate film so that space is released in the structure wherein a detachment-enhancing feature provided to the substrate film is configured to facilitate the removal of the at least a portion of the substrate film such that the adjacent remaining film material, if any, the arranged layer and the one or more first functional features are preserved and preferably remain substantially intact; and providing at least one second functional feature into the space released for use so that the at least one second functional feature operatively connects with at least one of the one or more first functional features.

公开(公告)号：US11166364B2

公开(公告)日：2021-11-02

申请号：US16833744

申请日：2020-03-30

Applicant: TACTOTEK OY

Inventor： Antti Keränen ,  Tomi Simula ,  Mikko Heikkinen ,  Jarmo Sääski ,  Pasi Raappana ,  Minna Pirkonen

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/28 ,  H05K5/06

Abstract: An electrical node includes a substrate for accommodating a functional element. The substrate includes a first side and an opposite second side, and hosting a number of connecting elements. The functional element includes an electronic component and conductive traces. The electrical node also includes a first material layer defining a protective covering. The first material layer defining at least a portion of the exterior surface of the nod arranged to reduce at least thermal expansion and/or mechanical deformation related stresses between one or more elements included in the node, adjacent the node and/or at least at a proximity thereto.

公开(公告)号：US11166363B2

公开(公告)日：2021-11-02

申请号：US16245643

申请日：2019-01-11

Applicant: TACTOTEK OY

Inventor： Antti Keränen ,  Tomi Simula ,  Mikko Heikkinen ,  Jarmo Sääski ,  Pasi Raappana ,  Minna Pirkonen

IPC: H05K1/02 ,  H05K1/18 ,  H05K5/06 ,  H05K3/28

Abstract: An electrical node includes a substrate for accommodating a functional element. The substrate includes a first side and an opposite second side, and hosting a number of connecting elements. The functional element includes an electronic component and conductive traces. The electrical node also includes a first material layer defining a protective covering. The first material layer defining at least a portion of the exterior surface of the nod arranged to reduce at least thermal expansion and/or mechanical deformation related stresses between one or more elements included in the node, adjacent the node and/or at least at a proximity thereto.

公开(公告)号：US12130005B2

公开(公告)日：2024-10-29

申请号：US18339427

申请日：2023-06-22

Applicant: TactoTek Oy

Inventor： Antti Keränen ,  Sami Torvinen ,  Tero Heikkinen ,  Pasi Korhonen ,  Pälvi Apilo ,  Mikko Heikkinen ,  Jarmo Sääski ,  Paavo Niskala ,  Ville Wallenius ,  Heikki Tuovinen ,  Janne Asikkala ,  Taneli Salmi ,  Suvi Kela ,  Outi Rusanen ,  Johanna Juvani ,  Mikko Sippari ,  Tomi Simula ,  Tapio Rautio ,  Samuli Yrjänä ,  Tero Rajaniemi ,  Simo Koivikko ,  Juha-Matti Hintikka ,  Hasse Sinivaara ,  Vinski Bräysy ,  Olimpia Migliore ,  Juha Sepponen

IPC: F21V7/28 ,  F21V7/00 ,  H05K1/02 ,  H05K1/18 ,  F21V7/10 ,  F21V8/00

CPC classification number: F21V7/00

Abstract: An integrated optically functional multilayer structure includes a flexible, substrate film arranged with a circuit design including at least a number of electrical conductors preferably additively printed on the substrate film; a light source provided upon a first side of the substrate film to internally illuminate at least portion of the structure for external perception; an optically transmissive plastic layer produced upon the first side of the substrate film, said plastic layer at least laterally surrounding, the light source, the substrate film at least having a similar or lower refractive index therewith; and a reflector design comprising at least one material layer, said reflector design being configured to reflect, the light emitted by the light source and incident upon the reflector design.

公开(公告)号：US10960641B2

公开(公告)日：2021-03-30

申请号：US17061934

申请日：2020-10-02

Applicant: TactoTek Oy

Inventor： Vinski Bräysy ,  Anne Isohätälä ,  Jarmo Sääski ,  Tomi Simula

IPC: B32B1/00 ,  B32B3/00 ,  B32B3/30 ,  B32B27/08 ,  G06F3/044 ,  B29L31/34 ,  B29C45/16

Abstract: A method for manufacturing an integrated multilayer structure for sensing applications, including obtaining at least one film including a sensing area; arranging the at least one film with reactance sensing electronics for sensing of one or more selected target quantities or qualities and conversion thereof into representative electrical signals, said sensing electronics including at least one sensing element and an electrical connection configured to connect the sensing element to an associated control circuitry; and molding or casting, and configuring, at least one plastic layer so that the plastic layer defines an integrated, intermediate layer between the sensing electronics and the sensing area and that the sensing area is superimposed with the sensing element of the sensing electronics, wherein it is further provided at least one physical feature to locally reduce the electrical distance between the sensing area and the sensing element to improve the associated sensing sensitivity.