公开(公告)号：US20250142876A1

公开(公告)日：2025-05-01

申请号：US19004098

申请日：2024-12-27

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Henry Litzmann Edwards ,  Curry Bachman Taylor

IPC: H10D30/65 ,  H10D64/00

Abstract: A microelectronic device includes a hybrid component. The microelectronic device has a substrate including silicon semiconductor material. The hybrid component includes a silicon portion in the silicon, and a wide bandgap (WBG) structure on the silicon. The WBG structure includes a WBG semiconductor material having a bandgap energy greater than a bandgap energy of the silicon. The hybrid component has a first current terminal on the silicon, and a second current terminal on the WBG semiconductor structure. The microelectronic device may be formed by forming the silicon portion of the hybrid component in the silicon, and subsequently forming the WBG structure on the silicon.

公开(公告)号：US11011510B2

公开(公告)日：2021-05-18

申请号：US16593251

申请日：2019-10-04

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/40

Abstract: An electronic device includes an ESD protection device with implanted regions that extend around a finger shape with a straight portion and elongated turn portions, and contacts that extend only in the straight portion, where the turn portions include elongated lightly doped implanted regions to mitigate turn on of a curvature PNP transistor for uniform device breakdown performance. Adjacent finger structures are spaced apart from one another to mitigate thermal transfer between device fingers.

公开(公告)号：US20210104514A1

公开(公告)日：2021-04-08

申请号：US16593416

申请日：2019-10-04

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon

IPC: H01L27/02 ,  H01L29/40 ,  H01L29/732 ,  H01L29/66 ,  H01L27/12

Abstract: An electronic device includes a silicon-on-insulator (SOI) structure, and an electrostatic discharge (ESD) protection device, with an isolation layer having a thickness and extending in a trench from a first implanted region. The ESD protection device includes a conductive field plate that extends over a portion of the first implanted region and past the first implanted region and over a portion of the isolation layer by an overlap distance that is 3.5 to 5.0 times the thickness of the isolation layer. In one example, the ESD protection device has a finger or racetrack shape, and the first implanted region and a second implanted region extend around first and second turn portions of the finger shape.

公开(公告)号：US10811533B2

公开(公告)日：2020-10-20

申请号：US15139496

申请日：2016-04-27

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Hideaki Kawahara ,  Simon John Molloy ,  Satoshi Suzuki ,  John Manning Savidge Neilson

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/786 ,  H01L21/311 ,  H01L29/10 ,  H01L29/417 ,  H01L29/45

Abstract: A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.

公开(公告)号：US10553717B2

公开(公告)日：2020-02-04

申请号：US15138955

申请日：2016-04-26

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Hideaki Kawahara ,  Simon John Molloy ,  Satoshi Suzuki ,  John Manning Savidge Neilson

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L21/311 ,  H01L29/10 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786

Abstract: A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.

公开(公告)号：US20170062573A1

公开(公告)日：2017-03-02

申请号：US15347325

申请日：2016-11-09

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Simon John Molloy ,  John Manning Savidge Neilson ,  Hideaki Kawahara

IPC: H01L29/40 ,  H01L29/10 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08

Abstract: A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region.

Abstract translation: 具有源区域，体接触区域和多个具有场板的沟槽结构的垂直高压MOS晶体管，以及形成MOS晶体管的方法通过减少MOS晶体管的导通电阻来降低 沟渠。 可以通过同时接触源区域，身体接触区域和场板的金属触点来减少沟槽间距。 也可以通过增加LDD区域的尺寸的栅极来减小沟槽间距。

公开(公告)号：US09496388B2

公开(公告)日：2016-11-15

申请号：US15069089

申请日：2016-03-14

Applicant: Texas Instruments Incorporated

Inventor： Thomas Eugene Grebs ,  Touhidur Rahman ,  Christopher Boguslaw Kocon

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/861 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/7813 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/861

Abstract: A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the semiconductor layer. The transistor cells include a first cell type including a first trench providing a first gate electrode or the first gate electrode is on the semiconductor surface between the first trench and a second trench, and a first source region is formed in the body region. The first gate electrode is electrically isolated from the first source region. A second cell type has a third trench providing a second gate electrode or the second gate electrode is on the semiconductor surface between the third trench and a fourth trench, and a second source region is in the body region. An electrically conductive member directly connects the second gate electrode, first source region and second source region together.

Abstract translation: 沟槽MOSFET器件包括第一掺杂类型的半导体层。 MOS晶体管单元处于半导体层中的第二掺杂类型的体区。 晶体管单元包括第一单元类型，包括提供第一栅电极的第一沟槽或者第一栅电极位于第一沟槽和第二沟槽之间的半导体表面上，并且第一源区形成在体区中。 第一栅电极与第一源区电隔离。 第二单元类型具有提供第二栅电极的第三沟槽，或者第二栅极位于第三沟槽和第四沟槽之间的半导体表面上，第二源极区在体区中。 导电构件将第二栅极电极，第一源极区域和第二源极区域直接连接在一起。

公开(公告)号：US20160197178A1

公开(公告)日：2016-07-07

申请号：US15069089

申请日：2016-03-14

Applicant: Texas Instruments Incorporated

Inventor： Thomas Eugene Grebs ,  Touhidur Rahman ,  Christopher Boguslaw Kocon

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/08 ,  H01L29/861

CPC classification number: H01L29/7813 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/861

Abstract: A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the semiconductor layer. The transistor cells include a first cell type including a first trench providing a first gate electrode or the first gate electrode is on the semiconductor surface between the first trench and a second trench, and a first source region is formed in the body region. The first gate electrode is electrically isolated from the first source region. A second cell type has a third trench providing a second gate electrode or the second gate electrode is on the semiconductor surface between the third trench and a fourth trench, and a second source region is in the body region. An electrically conductive member directly connects the second gate electrode, first source region and second source region together.

公开(公告)号：US20160197177A1

公开(公告)日：2016-07-07

申请号：US15069038

申请日：2016-03-14

Applicant: Texas Instruments Incorporated

Inventor： Thomas Eugene Grebs ,  Touhidur Rahman ,  Christopher Boguslaw Kocon

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/10 ,  H01L29/423 ,  H01L29/08 ,  H01L29/861

CPC classification number: H01L29/7813 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/861

Abstract: A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the semiconductor layer. The transistor cells include a first cell type including a first trench providing a first gate electrode or the first gate electrode is on the semiconductor surface between the first trench and a second trench, and a first source region is formed in the body region. The first gate electrode is electrically isolated from the first source region. A second cell type has a third trench providing a second gate electrode or the second gate electrode is on the semiconductor surface between the third trench and a fourth trench, and a second source region is in the body region. An electrically conductive member directly connects the second gate electrode, first source region and second source region together.

Abstract translation: 沟槽MOSFET器件包括第一掺杂类型的半导体层。 MOS晶体管单元处于半导体层中的第二掺杂类型的体区。 晶体管单元包括第一单元类型，包括提供第一栅电极的第一沟槽或者第一栅电极位于第一沟槽和第二沟槽之间的半导体表面上，并且第一源区形成在体区中。 第一栅电极与第一源区电隔离。 第二单元类型具有提供第二栅电极的第三沟槽，或者第二栅极位于第三沟槽和第四沟槽之间的半导体表面上，第二源极区在体区中。 导电构件将第二栅极电极，第一源极区域和第二源极区域直接连接在一起。

公开(公告)号：US20160163804A1

公开(公告)日：2016-06-09

申请号：US14563706

申请日：2014-12-08

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Simon John Molloy ,  John Manning Savidge Neilson ,  Hideaki Kawahara

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/404 ,  H01L21/763 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7827 ,  H01L29/783 ,  H01L29/7832

Abstract: A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region.

Abstract translation: 具有源区域，体接触区域和多个具有场板的沟槽结构的垂直高压MOS晶体管，以及形成MOS晶体管的方法通过减少MOS晶体管的导通电阻来降低 沟渠。 可以通过同时接触源区域，身体接触区域和场板的金属触点来减少沟槽间距。 也可以通过增加LDD区域的尺寸的栅极来减小沟槽间距。