公开(公告)号：US11777507B2

公开(公告)日：2023-10-03

申请号：US17865808

申请日：2022-07-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Debapriya Sahu ,  Rittu Sachdev

IPC: H03L7/093 ,  H03L7/083 ,  H03L7/095

CPC classification number: H03L7/093 ,  H03L7/083 ,  H03L7/095

Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.

公开(公告)号：US11303284B1

公开(公告)日：2022-04-12

申请号：US17375997

申请日：2021-07-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Debapriya Sahu ,  Rittu Sachdev

IPC: H03L7/089 ,  H03L7/099 ,  H03L7/08

Abstract: An integrated circuit device is provided. In some examples, the integrated circuit device includes a first re-timer configured to receive a reference clock signal and a voltage controlled oscillator (VCO) output signal, and the first re-timer is configured to provide a first re-timed clock signal in response to the reference clock signal and the VCO output signal. A multiplexer receives the first re-timed clock signal and provides a feedback clock signal. A phase frequency detector receives the feedback clock signal and the reference clock signal and provides an error signal in response to the feedback clock signal and the reference clock signal. A VCO receives a voltage signal based on the error signal, and the VCO is configured to provide the VCO output signal in response to the voltage signal.

公开(公告)号：US10924123B2

公开(公告)日：2021-02-16

申请号：US16219067

申请日：2018-12-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Debapriya Sahu ,  Rittu Sachdev

IPC: H03L7/06 ,  H03L7/093 ,  H03L7/083 ,  H03L7/095

Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.

公开(公告)号：US20190207560A1

公开(公告)日：2019-07-04

申请号：US16180879

申请日：2018-11-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Debapriya Sahu ,  Rohit Chatterjee

IPC: H03F1/02 ,  H03F3/21 ,  H03F3/193 ,  H03F3/45

CPC classification number: H03F1/0222 ,  H03F3/193 ,  H03F3/211 ,  H03F3/45179 ,  H03F2200/102 ,  H03F2200/171 ,  H03F2200/273 ,  H03F2200/378 ,  H03F2200/387 ,  H03F2200/393 ,  H03F2200/451 ,  H03F2203/21139 ,  H03F2203/21157 ,  H03H7/06

Abstract: One example includes a device that is comprised of a pre-power amplifier, a power amplifier, a signal path, and a dynamic bias circuit. The pre-power amplifier amplifies an input signal and outputs a first amplified signal. The power amplifier receives the first amplified signal and amplifies the first amplified signal based on a dynamic bias signal to produce a second amplified signal at an output thereof. The signal path is coupled between an output of the pre-power amplifier and an input of the power amplifier. The dynamic bias circuit monitors the first amplified signal, generates the dynamic bias signal, and outputs the dynamic bias into the signal path.

公开(公告)号：US20240380428A1

公开(公告)日：2024-11-14

申请号：US18783793

申请日：2024-07-25

Applicant: Texas Instruments Incorporated

Inventor： Debapriya Sahu ,  Rohit Chatterjee ,  Srinivas Venkata Veeramreddi

IPC: H04B1/44 ,  H04L27/36

Abstract: A wireless transceiver. The transceiver includes: (i) a transmit signal path; (ii) a calibration path, comprising a conductor to connect a calibration tone into the transmit signal path; (iii) a receive signal path, comprising a first data signal path to process a first data and a second data signal path, different than the first data signal path, to process a second data; (iv) a first capacitive coupling to couple a response to the calibration tone from the transmit signal path to the first data signal path; and (v) a second capacitive coupling to couple a response to the calibration tone from the transmit signal path to the second data signal path.

公开(公告)号：US12068774B2

公开(公告)日：2024-08-20

申请号：US18312720

申请日：2023-05-05

Applicant: Texas Instruments Incorporated

Inventor： Debapriya Sahu ,  Rohit Chatterjee ,  Srinivas Venkata Veeramreddi

IPC: H04B1/44 ,  H04L27/36

CPC classification number: H04B1/44 ,  H04L27/367

Abstract: A wireless transceiver. The transceiver includes: (i) a transmit signal path; (ii) a calibration path, comprising a conductor to connect a calibration tone into the transmit signal path; (iii) a receive signal path, comprising a first data signal path to process a first data and a second data signal path, different than the first data signal path, to process a second data; (iv) a first capacitive coupling to couple a response to the calibration tone from the transmit signal path to the first data signal path; and (v) a second capacitive coupling to couple a response to the calibration tone from the transmit signal path to the second data signal path.

公开(公告)号：US20230275614A1

公开(公告)日：2023-08-31

申请号：US18312720

申请日：2023-05-05

Applicant: Texas Instruments Incorporated

Inventor： Debapriya Sahu ,  Rohit Chatterjee ,  Srinivas Venkata Veeramreddi

IPC: H04B1/44 ,  H04L27/36

CPC classification number: H04B1/44 ,  H04L27/367

Abstract: A wireless transceiver. The transceiver includes: (i) a transmit signal path; (ii) a calibration path, comprising a conductor to connect a calibration tone into the transmit signal path; (iii) a receive signal path, comprising a first data signal path to process a first data and a second data signal path, different than the first data signal path, to process a second data; (iv) a first capacitive coupling to couple a response to the calibration tone from the transmit signal path to the first data signal path; and (v) a second capacitive coupling to couple a response to the calibration tone from the transmit signal path to the second data signal path.

公开(公告)号：US11418201B2

公开(公告)日：2022-08-16

申请号：US17146510

申请日：2021-01-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Debapriya Sahu ,  Rittu Sachdev

IPC: H03L7/093 ,  H03L7/083 ,  H03L7/095

Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.

公开(公告)号：US20250080067A1

公开(公告)日：2025-03-06

申请号：US18462083

申请日：2023-09-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Debapriya Sahu ,  Radhika Juluri ,  Meghna Agrawal

IPC: H03F3/24 ,  H03F1/08 ,  H04B1/04

Abstract: Embodiments disclosed herein relate to impedance matching for outputting wide-band signals in radio frequency applications. In an example, a circuit including a low-noise amplifier (LNA) sub-circuit and a tuning sub-circuit is provided. The LNA sub-circuit is configured to couple to an antenna and includes a transistor that includes a gate, a source, and a drain, a first inductor that includes a first terminal configured to couple to the antenna and includes a second terminal, a second inductor that includes a first terminal coupled to the first terminal of the first inductor and includes a second terminal coupled to the gate of the transistor, and a third inductor that includes a first terminal coupled to the source of the transistor and includes a second terminal. The tuning sub-circuit is coupled to the source of the transistor.

公开(公告)号：US11990916B2

公开(公告)日：2024-05-21

申请号：US17967815

申请日：2022-10-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Meghna Agrawal ,  Debapriya Sahu

IPC: H03M1/06 ,  H03M3/00

CPC classification number: H03M1/0617 ,  H03M3/464

Abstract: A circuit includes a digital-to-analog converter (DAC) and a compensation circuit. The DAC has first and second terminals. The compensation circuit includes a capacitor and a transistor. The capacitor has first and second terminals, with the first terminal of the capacitor coupled to the first terminal of the DAC. The transistor has a source coupled to the second terminal of the capacitor, and has a gate coupled to the second terminal of the DAC.