中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

51 records (took 0.02 seconds)

    GALLIUM-NITRIDE DEVICE FIELD-PLATE SYSTEM
    2.
    发明申请
    GALLIUM-NITRIDE DEVICE FIELD-PLATE SYSTEM 有权

    公开(公告)号：US20230101543A1

    公开(公告)日：2023-03-30

    申请号：US17491259

    申请日：2021-09-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Chang Soo Suh

    IPC: H01L29/40

    Abstract: One example described herein includes an integrated circuit (IC) that includes a gallium-nitride (GaN) transistor device. The IC includes GaN active layers that define an active region, and a gate structure arranged on a surface of the active region. The IC also includes a source arranged on a first side of the gate structure and a drain arranged on a second side of the gate structure. The IC further includes at least one source field-plate structure conductively coupled to the source and a gate-level field-plate structure that is coupled to the source.

    HEMT WAFER PROBE CURRENT COLLAPSE SCREENING
    5.
    发明申请
    HEMT WAFER PROBE CURRENT COLLAPSE SCREENING 审中-公开

    公开(公告)号：US20200064394A1

    公开(公告)日：2020-02-27

    申请号：US16400336

    申请日：2019-05-01

    Applicant: Texas Instruments Incorporated

    Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

    IPC: G01R31/26 ,  G01R27/26

    Abstract: A method includes applying a DC stress condition to a transistor for a predetermined stress time, measuring an impedance of the transistor after the predetermined stress time, and repeating the application of the DC stress condition and the measurement of the impedance until the measured impedance exceeds an impedance threshold or a total stress time exceeds a time threshold, where the DC stress condition includes applying a non-zero drain voltage signal to a drain terminal of the transistor, applying a gate voltage signal to a gate terminal of the transistor, and applying a non-zero source current signal to a source terminal of the transistor.

    Apparatus and methods for qualifying HEMT FET devices
    7.
    发明授权
    Apparatus and methods for qualifying HEMT FET devices 有权
    用于限定HEMT FET器件的装置和方法

    公开(公告)号：US09476933B2

    公开(公告)日：2016-10-25

    申请号：US14547849

    申请日：2014-11-19

    Applicant: Texas Instruments Incorporated

    Inventor： Jungwoo Joh ,  Srikanth Krishnan ,  Sameer Pendharkar

    IPC: G01R31/02 ,  G01R31/26 ,  H01L29/778 ,  H01L29/20

    CPC classification number: G01R31/2621 ,  H01L29/2003 ,  H01L29/7787

    Abstract: A method includes coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain terminal of the power transistor device under test; for a first set of test conditions, activating the drain pulse generator for each of the test conditions to apply a voltage pulse to the drain terminal, and for each of the test conditions, applying a voltage pulse to the gate terminal, the gate pulse rising only after the drain pulse falls below a predetermined threshold; for a second set of test conditions, applying a voltage pulse to the drain terminal, and applying a voltage pulse to the gate terminal, the drain pulse generator and the gate pulse generator both being active so that there is some overlap; and measuring the drain current into the power transistor device under test. An apparatus is disclosed.

    Abstract translation: 一种方法包括将栅极脉冲发生器耦合到被测功率晶体管器件的栅极端子，将漏极脉冲发生器耦合到被测功率晶体管器件的漏极端子; 对于第一组测试条件，激活用于每个测试条件的漏极脉冲发生器以向漏极端施加电压脉冲，并且对于每个测试条件，向栅极端施加电压脉冲，门脉冲上升 仅在漏极脉冲下降到预定阈值以下之前; 对于第二组测试条件，向漏极端子施加电压脉冲，并向栅极端施加电压脉冲，漏极脉冲发生器和栅极脉冲发生器都处于活动状态，使得存在一些重叠; 并测量进入被测功率晶体管器件的漏极电流。 公开了一种装置。

    FET dielectric reliability enhancement
    8.
    发明授权
    FET dielectric reliability enhancement 有权
    FET介质可靠性提高

    公开(公告)号：US09112011B2

    公开(公告)日：2015-08-18

    申请号：US14537455

    申请日：2014-11-10

    Applicant: Texas Instruments Incorporated

    Inventor： Asad Mahmood Haider ,  Jungwoo Joh

    IPC: H01L31/0256 ,  H01L29/778 ,  H01L29/51 ,  H01L29/66 ,  H01L29/20 ,  H01L21/28 ,  H01L21/285 ,  H01L29/49 ,  H01L29/45

    CPC classification number: H01L29/7787 ,  H01L21/28264 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/452 ,  H01L29/4975 ,  H01L29/518 ,  H01L29/66462

    Abstract: A semiconductor device may be formed by forming a silicon-containing gate dielectric layer over a semiconductor layer. A gate metal layer is formed over the gate dielectric layer; the gate metal layer includes 2 atomic percent to 10 atomic percent silicon during formation. The gate metal layer is patterned to form a metal gate. Source and drain contact holes are subsequently formed, and contact metal is formed and patterned in the contact holes. A subsequent contact anneal heats the contact metal and gate for at least 30 seconds at a temperature of at least 750° C.

    Abstract translation: 可以通过在半导体层上形成含硅栅极电介质层来形成半导体器件。 栅极金属层形成在栅极介质层上; 栅极金属层在形成期间包括2原子％至10原子％的硅。 栅极金属层被图案化以形成金属栅极。 随后形成源极和漏极接触孔，并在接触孔中形成接触金属并图案化。 随后的接触退火在至少750℃的温度下加热接触金属和栅极至少30秒。

    GROUP III-N DEVICE INCLUDING SOURCE CONTACT CONNECTED TO SUBSTRATE THROUGH TRENCH
    10.
    发明申请
    GROUP III-N DEVICE INCLUDING SOURCE CONTACT CONNECTED TO SUBSTRATE THROUGH TRENCH 有权

    公开(公告)号：US20250098266A1

    公开(公告)日：2025-03-20

    申请号：US18756202

    申请日：2024-06-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Zhikai Tang ,  Jungwoo Joh ,  Ujwal Radhakrishna

    IPC: H01L29/417 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

    Abstract: Semiconductor devices with a source contact extending into a substrate are described. In one example, a semiconductor device comprises a semiconductor substrate including a source region, a gate region, a drain region, and a drain access region, where a heterojunction structure is disposed over the semiconductor substrate. The heterojunction structure includes a buffer layer over the semiconductor substrate and a barrier layer over the buffer layer. A gate stack is disposed over the barrier layer in the gate region. A source contact in the source region extends into the semiconductor substrate, including a first contact with a 2DEG in the heterojunction structure and a second contact with the semiconductor substrate.

Patent Agency Ranking