公开(公告)号：US12164001B2

公开(公告)日：2024-12-10

申请号：US18368195

申请日：2023-09-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/317 ,  G01R31/28 ,  G01R31/3177 ,  G01R31/3183 ,  G01R31/3185

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

公开(公告)号：US20240402247A1

公开(公告)日：2024-12-05

申请号：US18799555

申请日：2024-08-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3185 ,  G06F11/26 ,  G06F11/267 ,  G06F11/27 ,  G06F11/34

Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

公开(公告)号：US12154835B2

公开(公告)日：2024-11-26

申请号：US17715006

申请日：2022-04-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/28 ,  G01R31/3185 ,  H01L21/66 ,  H01L23/48 ,  H01L25/065

Abstract: In one example, an integrated circuit comprises a die. The die has a first surface and a second surface, the second surface opposite to the first surface. The die also includes: a first contact on the first surface and a second contact on the second surface; a through silicon via having a first end and a second end, the first end coupled to the first contact and the second end coupled to the second contact; and a scan cell having a control input, a response input, and a stimulus output, the response input coupled to the first end and the stimulus output coupled to the second end.

公开(公告)号：US12092687B2

公开(公告)日：2024-09-17

申请号：US18373447

申请日：2023-09-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3177 ,  G01R31/3185 ,  G06F11/267 ,  G06F11/27 ,  G06F11/26 ,  G06F11/34

CPC classification number: G01R31/31723 ,  G01R31/31722 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318572 ,  G06F11/267 ,  G06F11/27 ,  G06F11/261 ,  G06F11/3466

Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

公开(公告)号：US12013434B2

公开(公告)日：2024-06-18

申请号：US18102955

申请日：2023-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3183 ,  G01R31/317 ,  G01R31/3177 ,  G01R31/3185 ,  G06F11/273

CPC classification number: G01R31/318335 ,  G01R31/3172 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318547 ,  G06F11/2733

Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

公开(公告)号：US12007441B2

公开(公告)日：2024-06-11

申请号：US18208366

申请日：2023-06-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3185 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/318555 ,  G01R31/31723 ,  G01R31/31724 ,  G01R31/31725 ,  G01R31/3177 ,  G01R31/318508 ,  G01R31/318513 ,  G01R31/318597

Abstract: This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.

公开(公告)号：US11835578B2

公开(公告)日：2023-12-05

申请号：US17579629

申请日：2022-01-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/28 ,  G01R31/317 ,  G06F11/27 ,  G01R31/3185 ,  G01R31/3177 ,  G06F11/267 ,  G06F11/26 ,  G06F11/34

CPC classification number: G01R31/31723 ,  G01R31/3177 ,  G01R31/31722 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/318572 ,  G06F11/267 ,  G06F11/27 ,  G06F11/261 ,  G06F11/3466

Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

公开(公告)号：US11835573B2

公开(公告)日：2023-12-05

申请号：US17557512

申请日：2021-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/28 ,  G01R31/3185 ,  H01L21/66 ,  H01L23/538 ,  H01L23/522 ,  H01L23/48

CPC classification number: G01R31/2853 ,  G01R31/2884 ,  G01R31/318541 ,  H01L22/34 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/481 ,  H01L2224/16146

Abstract: An integrated circuit die includes a substrate of semiconductor material having a top surface, a bottom surface, and an opening through the substrate between the top surface and the bottom surface. A through silicon via (TSV) has a conductive body in the opening, has a top contact point coupled to the body at the top surface, and has a bottom contact point coupled to the body at the bottom surface. A scan cell has a serial input, a serial output, control inputs, a voltage reference input, a response input coupled to one of the contact points, and a stimulus output coupled to the other one of the contact points.

公开(公告)号：US11808810B2

公开(公告)日：2023-11-07

申请号：US18111679

申请日：2023-02-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3185 ,  G06F11/26 ,  G01R31/3177 ,  H10K50/814 ,  H10K50/816 ,  H10K50/844 ,  H10K59/122 ,  H10K59/123 ,  H10K59/124 ,  H10K59/121 ,  H10K71/00 ,  G01R31/317 ,  H10K59/12 ,  H10K102/00 ,  H10K102/10 ,  H01L27/12

CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318555 ,  G01R31/318572 ,  G06F11/26 ,  H10K50/814 ,  H10K50/816 ,  H10K50/844 ,  H10K59/122 ,  H10K59/123 ,  H10K59/124 ,  H10K59/1213 ,  H10K71/00 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1248 ,  H10K59/1201 ,  H10K2102/00 ,  H10K2102/103

Abstract: In some examples, an integrated circuit comprises: a TDI input, a TDO output, a TCK input and a TMS input; a TAP state machine (TSM) having an input coupled to the TCK input, an input coupled to the TMS input, an instruction register control output, a TSM data register control (DRC) output, and a TSM state output; an instruction register having an input coupled to the TDI input, an output coupled to the TDO output, and a control input coupled to the instruction register control output of the TAP state machine; router circuitry including a TSM DRC input coupled to the TSM DRC output, a control DRC input coupled to the TSM state output, and a router DRC output; and a data register having an input coupled to the TDI input, an output coupled to the TDO output, and a data register DRC input coupled to the router DRC output.

公开(公告)号：US20230296670A1

公开(公告)日：2023-09-21

申请号：US18200047

申请日：2023-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/318533 ,  G01R31/31723 ,  G01R31/31725 ,  G01R31/31727

Abstract: The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.