Series connected ESD protection circuit

    公开(公告)号:US10192863B2

    公开(公告)日:2019-01-29

    申请号:US14221432

    申请日:2014-03-21

    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 2A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL 240) having a second conductivity type is formed below a face of the substrate. A first terminal (206) and a second terminal (204) are formed at a face of the substrate. A first ESD protection device (232) has a first current path between the first terminal and the buried layer. A second ESD protection device (216) has a second current path in series with the first current path and between the second terminal and the buried layer.

    Series connected ESD protection circuit

    公开(公告)号:US10930641B2

    公开(公告)日:2021-02-23

    申请号:US16210753

    申请日:2018-12-05

    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 2A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL 240) having a second conductivity type is formed below a face of the substrate. A first terminal (206) and a second terminal (204) are formed at a face of the substrate. A first ESD protection device (232) has a first current path between the first terminal and the buried layer. A second ESD protection device (216) has a second current path in series with the first current path and between the second terminal and the buried layer.

    SERIES CONNECTED ESD PROTECTION CIRCUIT
    4.
    发明申请
    SERIES CONNECTED ESD PROTECTION CIRCUIT 审中-公开
    系列连接的ESD保护电路

    公开(公告)号:US20150270257A1

    公开(公告)日:2015-09-24

    申请号:US14221432

    申请日:2014-03-21

    CPC classification number: H01L27/0262 H01L27/0259 H01L29/0649

    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 2A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL 240) having a second conductivity type is formed below a face of the substrate. A first terminal (206) and a second terminal (204) are formed at a face of the substrate. A first ESD protection device (232) has a first current path between the first terminal and the buried layer. A second ESD protection device (216) has a second current path in series with the first current path and between the second terminal and the buried layer.

    Abstract translation: 公开了一种用于集成电路的静电放电(ESD)保护电路(图2A)。 电路形成在具有第一导电类型的基板(P-EPI)上。 在衬底的表面下方形成具有第二导电类型的掩埋层(NBL 240)。 第一端子(206)和第二端子(204)形成在基板的表面。 第一ESD保护装置(232)在第一端子和埋层之间具有第一电流路径。 第二ESD保护装置(216)具有与第一电流路径串联的第二电流路径,以及在第二端子和埋层之间。

    SERIES CONNECTED ESD PROTECTION CIRCUIT
    5.
    发明申请

    公开(公告)号:US20190109128A1

    公开(公告)日:2019-04-11

    申请号:US16210753

    申请日:2018-12-05

    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 2A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL 240) having a second conductivity type is formed below a face of the substrate. A first terminal (206) and a second terminal (204) are formed at a face of the substrate. A first ESD protection device (232) has a first current path between the first terminal and the buried layer. A second ESD protection device (216) has a second current path in series with the first current path and between the second terminal and the buried layer.

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