公开(公告)号：US12174658B2

公开(公告)日：2024-12-24

申请号：US17892860

申请日：2022-08-22

Applicant: Texas Instruments Incorporated

Inventor： Shailesh Ghotgalkar ,  Rajeev Suvarna ,  Prasanth Viswanathan Pillai ,  Saravanan G

IPC: G06F1/08 ,  G06F1/12 ,  G06F11/16 ,  H03K5/135 ,  H03K5/26

Abstract: An example device comprising: first clock divider circuitry to be coupled to a first clock; first counter circuitry configured to be coupled to the first clock divider circuitry, the first counter circuitry configured to increment based on the first clock and a second clock; second clock divider circuitry to be coupled to a third clock; second counter circuitry configured to be coupled to the second clock divider circuitry, the second counter circuitry configured to increment based on the third clock and the second clock; and comparison circuitry coupled to the first and second counter circuitry.

公开(公告)号：US12130329B2

公开(公告)日：2024-10-29

申请号：US18115739

申请日：2023-02-28

Applicant: Texas Instruments Incorporated

Inventor： Prasanth Viswanathan Pillai ,  Swathi Gangasani ,  Vaskar Sarkar

IPC: G01R31/3177 ,  G01R31/3167 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/3167 ,  G01R31/318508 ,  G01R31/318533 ,  G01R31/318536

Abstract: An example apparatus includes a buffer configured to, when enabled: obtain an input voltage; and provide the input voltage to a first boundary cell; and a second boundary cell configured to, when the apparatus is used in analog mode and a boundary scan occurs disable the buffer.

公开(公告)号：US12119826B2

公开(公告)日：2024-10-15

申请号：US17849417

申请日：2022-06-24

Applicant: Texas Instruments Incorporated

Inventor： Srinivasa Chakravarthy ,  Prasanth Viswanathan Pillai ,  Mohammed Arif ,  Bhargov Bora

IPC: H03K5/00 ,  G06F1/06 ,  G06F11/263 ,  H03K21/02

CPC classification number: H03K5/00006 ,  G06F1/06 ,  G06F11/263 ,  H03K21/02

Abstract: An example apparatus includes multiplexer circuitry configured to couple a communication module to at least one of a data bus input or a test signal; and embedded pattern generator (EPG) circuitry coupled to the multiplexer circuitry, the EPG circuitry including: clock divider circuitry including a plurality of clock outputs, the clock divider circuitry configured to be coupled to an output of a clock, the plurality of clock outputs configured to be of a frequency equal to a division of a frequency of the output of the clock; a multiplexer including a multiplexer output, the multiplexer configured to couple one of the plurality of clock outputs to the multiplexer output; and signal generator circuitry including an input clock, an EPG input, and a plurality of data outputs, the input clock coupled to the multiplexer output, the signal generator circuitry configured to generate a data stream.

公开(公告)号：US20180321305A1

公开(公告)日：2018-11-08

申请号：US15584550

申请日：2017-05-02

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Earl Stafford ,  Prasanth Viswanathan Pillai ,  Ashish Arvind Vanjari

IPC: G01R31/28 ,  G01R31/00 ,  G01R31/3187 ,  G01D3/08

CPC classification number: G01R31/2856 ,  B60T8/885 ,  B60T2270/406 ,  B60T2270/411 ,  B60T2270/413 ,  G01D3/08 ,  G01R31/007 ,  G01R31/2829 ,  G01R31/3187

Abstract: An integrated circuit (IC) chip for providing a safety-critical value includes first and second processing paths. The first processing path includes a first processing element and is coupled to receive a first input signal on a first input pin and to provide a first output signal that provides the safety-critical value on an output pin. The second processing path includes a second processing element and is coupled to receive a second input signal and to provide a second output signal. The first processing path and the second processing path are independent of each other. A smart comparator on the IC chip receives the first output signal and the second output signal and initiates a remedial action responsive to a difference between the first output signal and the second output signal reaching a configurable threshold.

公开(公告)号：US20230213958A1

公开(公告)日：2023-07-06

申请号：US17892860

申请日：2022-08-22

Applicant: Texas Instruments Incorporated

Inventor： Shailesh Ghotgalkar ,  Rajeev Suvarna ,  Prasanth Viswanathan Pillai ,  Saravanan G

IPC: G06F1/08 ,  G06F1/12 ,  H03K5/26 ,  H03K5/135

CPC classification number: G06F1/08 ,  G06F1/12 ,  H03K5/26 ,  H03K5/135

Abstract: An example device comprising: first clock divider circuitry to be coupled to a first clock; first counter circuitry configured to be coupled to the first clock divider circuitry, the first counter circuitry configured to increment based on the first clock and a second clock; second clock divider circuitry to be coupled to a third clock; second counter circuitry configured to be coupled to the second clock divider circuitry, the second counter circuitry configured to increment based on the third clock and the second clock; and comparison circuitry coupled to the first and second counter circuitry.

公开(公告)号：US20230068811A1

公开(公告)日：2023-03-02

申请号：US18047511

申请日：2022-10-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prasanth Viswanathan Pillai ,  Rajeev Suvarna ,  Saya Goud Langadi ,  Shailesh Ganapat Ghotgalkar

IPC: G01R31/3177 ,  H03K5/24 ,  H03K19/003 ,  H03K3/037

Abstract: Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

公开(公告)号：US10168992B1

公开(公告)日：2019-01-01

申请号：US15671679

申请日：2017-08-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prasanth Viswanathan Pillai ,  Venkatesh Natarajan ,  Alexander Tessarolo

IPC: G06F7/544 ,  G06F7/483

Abstract: Processor architectures and associated methods provide interruptible, instruction-based trigonometric function computation based on CORDIC iterations, receiving and outputting floating-point values (e.g., 64-bit). The architectures and methods can provide multiple CORDIC-like iterations in as little as a single CPU processing cycle to provide an overall faster execution of trigonometric operations while having zero additional overhead for service of time-critical interrupts. Post interrupt service, a CORDIC operation can be resumed from where it was interrupted.

公开(公告)号：US10062451B2

公开(公告)日：2018-08-28

申请号：US15346737

申请日：2016-11-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prasanth Viswanathan Pillai ,  Saya Goud Langadi

IPC: G11C29/42 ,  G06F11/10 ,  G11C29/44 ,  H03M13/09 ,  G11C29/14 ,  G11C29/16 ,  G11C29/32 ,  G11C29/12 ,  G11C29/18 ,  G11C29/40

CPC classification number: G11C29/42 ,  G06F11/1048 ,  G06F11/106 ,  G06F11/1068 ,  G11C29/14 ,  G11C29/16 ,  G11C29/32 ,  G11C29/44 ,  G11C2029/1208 ,  G11C2029/1806 ,  G11C2029/4002 ,  H03M13/09 ,  H03M13/093

Abstract: A schedulable memory scrubbing circuit and/or a known-state memory test circuit (collectively, background memory test apparatus (“BGMTA”)) are located on-chip with an integrated computing system. The BGMTA operates in parallel with a system CPU but shares a system bus with the CPU. The BGMTA sequentially reads one word at a time from a block of memory to be tested during system bus idle cycles. The schedulable memory scrubbing circuit embodiment tests on-chip parity/ECC memory arrays using memory controller-implemented parity or ECC error detection to trigger error handling interrupts. The known-state memory test circuit embodiment performs CRC calculations on known-state memory arrays as each data word is read sequentially. A final resulting CRC calculation value is compared to a known CRC value for the block, sometimes referred to as a “golden CRC.” If the two CRC values differ, a CRC error interrupt is triggered for servicing by the CPU.

公开(公告)号：US20170133106A1

公开(公告)日：2017-05-11

申请号：US15346737

申请日：2016-11-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prasanth Viswanathan Pillai ,  Saya Goud Langadi

IPC: G11C29/42 ,  G11C29/44 ,  H03M13/09 ,  G06F11/10

CPC classification number: G11C29/42 ,  G06F11/106 ,  G06F11/1068 ,  G11C29/14 ,  G11C29/16 ,  G11C29/32 ,  G11C29/44 ,  G11C2029/1208 ,  G11C2029/1806 ,  G11C2029/4002 ,  H03M13/09 ,  H03M13/093

Abstract: A schedulable memory scrubbing circuit and/or a known-state memory test circuit (collectively, background memory test apparatus (“BGMTA”)) are located on-chip with an integrated computing system. The BGMTA operates in parallel with a system CPU but shares a system bus with the CPU. The BGMTA sequentially reads one word at a time from a block of memory to be tested during system bus idle cycles. The schedulable memory scrubbing circuit embodiment tests on-chip parity/ECC memory arrays using memory controller-implemented parity or ECC error detection to trigger error handling interrupts. The known-state memory test circuit embodiment performs CRC calculations on known-state memory arrays as each data word is read sequentially. A final resulting CRC calculation value is compared to a known CRC value for the block, sometimes referred to as a “golden CRC.” If the two CRC values differ, a CRC error interrupt is triggered for servicing by the CPU.

公开(公告)号：US20250052813A1

公开(公告)日：2025-02-13

申请号：US18929471

申请日：2024-10-28

Applicant: Texas Instruments Incorporated

Inventor： Prasanth Viswanathan Pillai ,  Swathi Gangasani ,  Vaskar Sarkar

IPC: G01R31/3177 ,  G01R31/3167 ,  G01R31/3185

Abstract: An example apparatus includes a buffer configured to, when enabled: obtain an input voltage; and provide the input voltage to a first boundary cell; and a second boundary cell configured to, when the apparatus is used in analog mode and a boundary scan occurs disable the buffer.