公开(公告)号：US12267182B2

公开(公告)日：2025-04-01

申请号：US18117511

申请日：2023-03-06

Applicant: Texas Instruments Incorporated

Inventor： Raghu Ganesan ,  Saravanakkumar Radhakrishnan ,  Gaurav Aggarwal

IPC: H04L12/40 ,  H04L25/03

Abstract: A receiver circuit includes a feedback loop including a device. The receiver circuit also includes a register and a sequencer. The sequencer is configured to, responsive to an error signal being below a threshold value, cause the register to store a value indicative of the state of the feedback loop. The sequencer is also configured to cause the feedback loop to transition to a lower power state, and, responsive to a detected wake-up event, cause the previously stored value indicative of the state of the feedback loop to be loaded from the register into the device and enable the feedback loop.

公开(公告)号：US20230208685A1

公开(公告)日：2023-06-29

申请号：US18111862

申请日：2023-02-20

Applicant: Texas Instruments Incorporated

Inventor： Raghu Ganesan ,  Saravanakkumar Radhakrishnan ,  Gaurav Aggarwal

IPC: H04L25/03 ,  H04L7/00 ,  H04L7/033

CPC classification number: H04L25/03057 ,  H04L7/0079 ,  H04L7/033

Abstract: An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.

公开(公告)号：US11374601B2

公开(公告)日：2022-06-28

申请号：US17200426

申请日：2021-03-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raghu Ganesan ,  Saravanakkumar Radhakrishnan ,  Kalpesh Laxmanbhai Rajai ,  Soumyajit Roul ,  Sumantra Seth

IPC: H04B1/10 ,  H04B1/12 ,  H04B1/16 ,  H03M1/00 ,  H03M1/06 ,  H03M1/50

Abstract: A receiver circuit includes an interleaved ADC, a first delay circuit, a second delay circuit, a first processing channel, a second processing channel, and an interleaving ADC timing error detector circuit. The interleaved ADC includes a first ADC and a second ADC in parallel. The first delay circuit delays a first clock signal provided to the first ADC. The second delay circuit delays a second clock signal provided to the second ADC. The first processing channel processes data samples provided by the first ADC, and includes a first slicer. The second processing channel processes data samples provided by the second ADC, and includes a second slicer. The interleaving ADC timing error detector circuit controls delay of the first delay circuit and the second delay circuit based on an output signal of the first slicer, and an output signal or an input signal of the second slicer.

公开(公告)号：US11316707B2

公开(公告)日：2022-04-26

申请号：US17199142

申请日：2021-03-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kalpesh Laxmanbhai Rajai ,  Saravanakkumar Radhakrishnan ,  Gaurav Aggarwal ,  Raghu Ganesan ,  Rallabandi V Lakshmi Annapurna

IPC: H04L25/03 ,  H04L12/12 ,  H03H17/06

Abstract: A method includes receiving an input signal at a filter, where the filter includes a plurality of filter taps, and where each of a first filter tap and a second filter tap has a weighting coefficient. The method also includes shutting down the first filter tap based on the weighting coefficient of the first filter tap being below a threshold and the weighting coefficient of the second filter tap being below the threshold, where the second filter tap is next to the first filter tap.

公开(公告)号：US20220038061A1

公开(公告)日：2022-02-03

申请号：US17501212

申请日：2021-10-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raghu Ganesan ,  Harish Kumar Ramesh ,  John Roshan Samuel Chandran ,  Lakshmi Bala Krishna Manoja Vinnakota

IPC: H03F1/32 ,  H04B1/04 ,  H04B17/12

Abstract: A method for digital predistortion (DPD) calibration in a wireless communication device is provided that includes transmitting, by transmission circuitry of the wireless communication device, a plurality of pulses, where each pulse corresponds to an amplitude step in a pattern of amplitude steps, where the amplitude steps are separated by silence gaps, receiving each pulse in receiver circuitry of the wireless communication device, generating, by an accumulator component of the wireless communication device, an accumulated sample for each pulse based on a plurality of samples output by the receiver circuitry for the pulse, and computing, by a processor of the wireless communication device, amplitude dependent gain (AM/AM) and amplitude dependent phase shift (AM/PM) values for each accumulated sample.

公开(公告)号：US10833895B2

公开(公告)日：2020-11-10

申请号：US16575151

申请日：2019-09-18

Applicant: Texas Instruments Incorporated

Inventor： Raghu Ganesan ,  Kalpesh Laxmanbhai Rajai ,  Saravanakkumar Swaminathan Radhakrishnan

IPC: H03K5/159 ,  H04L25/03 ,  H04B1/16

Abstract: A device includes a receiver having analog front-end circuitry and a digital signal processing (DSP) circuit. The DSP circuit is configured to select one of a plurality of digital equalization (DEQ) filter options and to perform DEQ operations based on the selected DEQ filter option, wherein the DSP circuit is configured to select one of the plurality of DEQ filter options based on a channel length estimate and a plurality of different sets of DEQ filter coefficients predetermined for different channel lengths.

公开(公告)号：US20200041551A1

公开(公告)日：2020-02-06

申请号：US16597612

申请日：2019-10-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Tom Altus ,  Karthik Subburaj ,  Sreekiran Samala ,  Raghu Ganesan

IPC: G01R23/02 ,  G01R23/10

Abstract: A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.

公开(公告)号：US20240106688A1

公开(公告)日：2024-03-28

申请号：US17954463

申请日：2022-09-28

Applicant: Texas Instruments Incorporated

Inventor： Saravanakkumar Radhakrishnan ,  Raghu Ganesan

IPC: H04L25/03 ,  H04L7/00

CPC classification number: H04L25/03267 ,  H04L7/0062

Abstract: A network communications receiver and a method of operating the same in symbol timing recovery and equalization adaptation. A data converter samples a received analog signal at an initialization frequency higher than the symbol frequency of the received signal, and converts the samples to a digital sample stream. A decision feedback equalizer including a digital filter with one or more tap weights is adapted, and an error measurement obtained from the output of the decision feedback equalizer. In response to the error measurement crossing an error threshold value, a timing loop including timing error detection is initiated to adjust the phase of the sampling clock applied to the data converter.

公开(公告)号：US11876648B2

公开(公告)日：2024-01-16

申请号：US17733843

申请日：2022-04-29

Applicant: Texas Instruments Incorporated

Inventor： Raghu Ganesan ,  Kalpesh Rajai

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03267

Abstract: Disclosed embodiments include a decision feedback equalizer (DFE) comprising an N-bit parallel input adapted to be coupled to a communication channel and configured to receive consecutive communication symbols, a first DFE path including a first path input configured to receive communication symbols, and a first adder having a first adder input coupled to the first path input. There is a first DFE filter having outputs responsive to the first DFE filter inputs, the outputs coupled to the second adder input. The DFE includes a first path having a first slicer and a first multiplexer, a first path multiplexer output, and a second DFE path including a second path input configured to receive a second communication symbol, a second adder, a second DFE filter, a second slicer, and a second multiplexer.

公开(公告)号：US11695539B1

公开(公告)日：2023-07-04

申请号：US17587241

申请日：2022-01-28

Applicant: Texas Instruments Incorporated

Inventor： Geet Govind Modi ,  Sumantra Seth ,  Vikram Sharma ,  Shankar Ramakrishnan ,  Raghu Ganesan

IPC: H04B1/38 ,  H04L5/16 ,  H04L7/033 ,  H04L7/06 ,  H04L7/00 ,  H03K19/173 ,  H04L7/04 ,  H03K19/17784

CPC classification number: H04L7/033 ,  H03K19/1737 ,  H03K19/17784 ,  H04L7/0079 ,  H04L7/0091 ,  H04L7/048 ,  H04L7/065

Abstract: A physical layer transceiver and a network node including the transceiver. The transceiver includes a media independent interface, a converter circuit block comprising circuitry configured to convert digital signals to analog signals for transmission over a network communications medium and convert analog signals received over the medium to digital signals, and one or more processing blocks configured to process digital data communicated between the media independent interface and the converter circuit block according to a network protocol. Management and control circuitry including power management circuitry and reset circuitry are provided. The transceiver further includes at least one single event effect (SEE) monitor, such as an ambience monitor, a configuration register monitor, a state machine monitor, or a phase locked loop (PLL) lock monitor, configured to detect and respond to an SEE event in the transceiver.