HUB FOR MULTI-CHIP SENSOR SYSTEMS

    公开(公告)号:US20250130737A1

    公开(公告)日:2025-04-24

    申请号:US18991960

    申请日:2024-12-23

    Abstract: Various systems and methods are provided. One such system includes first and second inputs of first and second types, respectively; a data controller, including a context mapper coupled to the first and second inputs. The data controller includes a context mapper that provides a processing identifier and a storage identifier to each item of data received from the first and second inputs; and a set of processing components, each coupled to the context mapper, and each associated with a respective processing identifier for processing each item of data having the corresponding processing identifier. The system further includes a memory coupled to the context mapper, the memory having multiple storage locations each associated with a respective storage identifier for storing each item of data having the corresponding storage identifier; and first and second outputs of the first and second types, respectively, coupled to the data controller.

    HUB FOR MULTI-CHIP SENSOR SYSTEMS
    6.
    发明公开

    公开(公告)号:US20240192884A1

    公开(公告)日:2024-06-13

    申请号:US18585619

    申请日:2024-02-23

    Abstract: Various systems and circuits are provided. One such system includes input interfaces to receive items of input data of different types; output interfaces, each of a different type; an interconnect coupled to the input interfaces and to the output interfaces; and an multichip hub that includes buffers respectively corresponding to the types of input data, context memory blocks, and a data movement engine with a context mapper to determine a context of each item of input data received and provide the item of input data to a corresponding context memory block. Multiple processing blocks within the multichip hub are each configured to perform a respective processing operation. The data movement engine receives context configuration data to determine, for each item of input data received, which of the multiple processing operations are to be applied to the item of input data.

    Configurable multi-function PCIe endpoint controller in an SoC

    公开(公告)号:US11314673B2

    公开(公告)日:2022-04-26

    申请号:US17134861

    申请日:2020-12-28

    Abstract: A configurable multi-function Peripheral Component Interchange Express (PCIe) endpoint controller, integrated in a system-on-chip (SoC), that exposes multiple functions of multiple processing subsystems (e.g., peripherals) to a host. The SoC may include a centralized transaction tunneling unit and a multi-function interrupt manager. The processing subsystems output data to the host via the centralized transaction tunneling unit, which translates addresses provided by the host to a local address of the SoC. Therefore, the centralized transaction tunneling unit enables those processing subsystems to consume addresses provided by the host without the need for software intervention and software-based translation. The SoC may also provide isolation between each function provided by the processing systems. The multi-function interrupt manager enables the endpoint controller to propagate interrupt messages received from the processing subsystems to the host.

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