公开(公告)号：US20220367444A1

公开(公告)日：2022-11-17

申请号：US17503877

申请日：2021-10-18

Applicant: Texas Instruments Incorporated

Inventor： Robert Martin Higgins ,  Xiaoju Wu ,  Li Wang ,  Venugopal Balakrishna Menon

IPC: H01L27/06 ,  H01L49/02 ,  H01L21/762

Abstract: A method of manufacturing an electronic device includes forming a shallow trench isolation (STI) structure on or in a semiconductor surface layer and forming a mask on the semiconductor surface layer, where the mask exposes a surface of a dielectric material of the STI structure and a prospective local oxidation of silicon (LOCOS) portion of a surface of the semiconductor surface layer. The method also includes performing an oxidation process using the mask to oxidize silicon in an indent in the dielectric material of the STI structure and to grow an oxide material on the exposed LOCOS portion of the surface of the semiconductor surface layer.

公开(公告)号：US20200161471A1

公开(公告)日：2020-05-21

申请号：US16750020

申请日：2020-01-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xiaoju Wu ,  Robert James Todd ,  Henry Litzmann Edwards

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/285 ,  H01L21/225 ,  H01L21/324 ,  H01L21/265 ,  H01L21/762 ,  H01L21/74 ,  H01L29/10 ,  H01L29/40 ,  H01L29/06

Abstract: A semiconductor device includes a local oxidation of silicon (LOCOS) structure and a shallow trench isolation (STI) structure formed over a semiconductor substrate. A source region is located between the LOCOS structure and the STI structure. A gate structure is located between the source region and the LOCOS structure. A contact may be located over the STI structure electrically connect to the gate structure.

公开(公告)号：US10461182B1

公开(公告)日：2019-10-29

申请号：US16021772

申请日：2018-06-28

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  James Robert Todd ,  Binghua Hu ,  Xiaoju Wu ,  Stephanie L. Hilbun

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10

Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods therefor, including a multi-fingered transistor structure formed in an active region of a semiconductor substrate, in which a transistor drain finger is centered in a multi-finger transistor structure, a transistor body region laterally surrounds the transistor, an outer drift region laterally surrounds an active region of the semiconductor substrate, and one or more inactive or dummy structures are formed at lateral ends of the transistor finger structures.

公开(公告)号：US20190214471A1

公开(公告)日：2019-07-11

申请号：US16354550

申请日：2019-03-15

Applicant: Texas Instruments Incorporated

Inventor： Xiaoju Wu

IPC: H01L29/423 ,  H01L29/10 ,  H01L29/06 ,  H01L29/78

Abstract: In at least some embodiments, a semiconductor device comprises a source region is formed within a well. The source region comprises a first dopant type, and the well comprises a second dopant type opposite the first dopant type. A termination region is formed within the well, the termination region being aligned with the source region and having an end adjacent to and spaced apart from an end of the source region. The termination region comprises a semiconducting material having the second dopant type. A preselected concentration value of the dopant in the termination region is greater than a concentration value of the second dopant type in the well.

公开(公告)号：US10347732B1

公开(公告)日：2019-07-09

申请号：US16354550

申请日：2019-03-15

Applicant: Texas Instruments Incorporated

Inventor： Xiaoju Wu

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/4238 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/66727 ,  H01L29/7811 ,  H01L29/7835

Abstract: In at least some embodiments, a semiconductor device comprises a source region is formed within a well. The source region comprises a first dopant type, and the well comprises a second dopant type opposite the first dopant type. A termination region is formed within the well, the termination region being aligned with the source region and having an end adjacent to and spaced apart from an end of the source region. The termination region comprises a semiconducting material having the second dopant type. A preselected concentration value of the dopant in the termination region is greater than a concentration value of the second dopant type in the well.

公开(公告)号：US20180350795A1

公开(公告)日：2018-12-06

申请号：US16054037

申请日：2018-08-03

Applicant: Texas Instruments Incorporated

Inventor： Akram A. Salman ,  Farzan Farbiz ,  Amitava Chatterjee ,  Xiaoju Wu

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/10

CPC classification number: H01L27/0262 ,  H01L29/1012 ,  H01L29/7424 ,  H01L29/7436

Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

公开(公告)号：US20180350794A1

公开(公告)日：2018-12-06

申请号：US16053985

申请日：2018-08-03

Applicant: Texas Instruments Incorporated

Inventor： Akram A. Salman ,  Farzan Farbiz ,  Amitava Chatterjee ,  Xiaoju Wu

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/10

CPC classification number: H01L27/0262 ,  H01L29/1012 ,  H01L29/7424 ,  H01L29/7436

Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

公开(公告)号：US10083951B2

公开(公告)日：2018-09-25

申请号：US14750339

申请日：2015-06-25

Applicant: Texas Instruments Incorporated

Inventor： Akram A. Salman ,  Farzan Farbiz ,  Amitava Chatterjee ,  Xiaoju Wu

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/74

Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

公开(公告)号：US09899376B2

公开(公告)日：2018-02-20

申请号：US15060736

申请日：2016-03-04

Applicant: Texas Instruments Incorporated

Inventor： Xiaoju Wu ,  C. Matthew Thompson

IPC: H01L29/10 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/0638 ,  H01L29/0847 ,  H01L29/1033

Abstract: An integrated circuit with transistor regions formed on a substrate. Each transistor region includes a channel region and a terminal region. The channel region is positioned along a traverse dimension, and it includes a channel edge region along a longitudinal dimension. The terminal region is positioned adjacent to the channel region, and it is doped with a first dopant of a first conductivity type. Each transistor region may include an edge block region, which is positioned along the longitudinal dimension and adjacent to the channel edge region. The edge block region is doped with a second dopant of a second conductivity type opposite to the first conductivity type. The channel region doped with a dopant and having a first doping concentration. Each transistor region may include an edge recovery region overlapping with the channel edge region and having a second doping concentration higher than the first doping concentration.

公开(公告)号：US20140124828A1

公开(公告)日：2014-05-08

申请号：US13668022

申请日：2012-11-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Akram A. Salman ,  Farzan Farbiz ,  Amitava Chatterjee ,  Xiaoju Wu

IPC: H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/1012 ,  H01L29/7424 ,  H01L29/7436

Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

Abstract translation: 公开了一种用于集成电路的半导体可控整流器（图4A）。 半导体可控整流器包括具有第一导电类型（N）的第一轻掺杂区域（100）和在第一轻掺杂区域内形成的具有第二导电类型（P）的第一重掺杂区域（108）。 具有第二导电类型的第二轻掺杂区域（104）形成在第一轻掺杂区域附近。 在第二轻掺杂区域内形成具有第一导电类型的第二重掺杂区域（114）。 具有第一导电类型的掩埋层（101）形成在第二轻掺杂区域的下方并且电连接到第一轻掺杂区域。 在第二轻掺杂区域和第三重掺杂区域之间形成具有第二导电类型的第三轻掺杂区域（102）。 具有第二导电类型的第四轻掺杂区域（400）形成在第二轻掺杂区域和第三重掺杂区域之间，并且电连接到第二和第三轻掺杂区域。