公开(公告)号：US20240429290A1

公开(公告)日：2024-12-26

申请号：US18751877

申请日：2024-06-24

Applicant: Texas Instruments Incorporated

Inventor： Ya Ping Chen ,  Yunlong Liu ,  Hong Yang ,  Jing Hu ,  Chao Zhuang ,  Peng Li ,  Sheng Pin Yang

IPC: H01L29/40 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device includes etching a first trench and a second trench in an epitaxial layer over a semiconductor and forming a dielectric liner within the trenches. A photoresist layer is formed within the trenches and over the epitaxial layer and given a post-exposure bake at a first temperature. The photoresist layer is then given an adhesion-promoting bake at a greater second temperature; The photoresist layer is then removed from a top portion the trenches, thereby exposing a top portion of the dielectric liner and leaving a remaining portion of the photoresist in a bottom portion of the trenches. The exposed dielectric liner is etched, thereby leaving a remaining portion of the dielectric liner in the top portion of the trenches. The remaining portion of the photoresist is removed and the trenches are filled with a polysilicon layer.

公开(公告)号：US11888021B2

公开(公告)日：2024-01-30

申请号：US17489199

申请日：2021-09-29

Applicant: Texas Instruments Incorporated

Inventor： Jing Hu ,  Zhi Peng Feng ,  Chao Zuo ,  Dongsheng Liu ,  Yunlong Liu ,  Manoj K Jain ,  Shengpin Yang

IPC: H01L21/762 ,  H01L49/02 ,  H01L21/324 ,  H01L21/225 ,  H01L21/74 ,  H01L29/94 ,  H01L21/3215

CPC classification number: H01L28/87 ,  H01L21/2253 ,  H01L21/324 ,  H01L21/32155 ,  H01L21/743 ,  H01L21/76237 ,  H01L28/40 ,  H01L29/945

Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.

公开(公告)号：US11532560B2

公开(公告)日：2022-12-20

申请号：US14531177

申请日：2014-11-03

Applicant: Texas Instruments Incorporated

Inventor： Yunlong Liu ,  Yufei Xiong ,  Hong Yang

IPC: H01L23/532 ,  H01L23/485 ,  H01L21/768 ,  H01L21/311

Abstract: In a semiconductor process, a seamless tungsten plug is formed in an inter-layer dielectric by forming the inter-layer dielectric from multiple oxide layers having different wet etch rates, from lowest wet-etch rate for the lowest layer to highest wet-etch rate for the highest layer, forming a hole or trench in the inter-layer dielectric using a dry etch process, reconfiguring the hole or trench to have sloped side walls by performing a wet etch step, and filling the hole or trench with tungsten and etching back the tungsten to form a seamless tungsten plug.

公开(公告)号：US20220093754A1

公开(公告)日：2022-03-24

申请号：US17167911

申请日：2021-02-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Peng Li ,  Ya ping Chen ,  Yunlong Liu ,  Hong Yang ,  Shengpin Yang ,  Jing Hu ,  Chao Zhuang

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A method (200) of fabricating a semiconductor device includes etching (205) a group of trenches in a semiconductor surface layer of a substrate. The group of trenches includes an outermost trench that has a first width and remaining trenches of the group of trenches have a second width that is less than the first width. The outermost trench is formed at an edge of the group of trenches. A dielectric liner is formed (210) in the group of trenches and the dielectric liner is etched (215) in an upper portion of the group of trenches to remove a partial thickness of the dielectric liner. A full thickness of the dielectric liner is maintained in a lower portion of the group of trenches. The group of trenches is filled (220) with a polysilicon layer.

公开(公告)号：US10720490B2

公开(公告)日：2020-07-21

申请号：US16732371

申请日：2020-01-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： He Lin ,  Jiao Jia ,  Yunlong Liu ,  Manoj Jain

IPC: H01L49/02 ,  H01L21/02 ,  H01L23/495 ,  H01L29/94

Abstract: A trench capacitor includes at least one epitaxial semiconductor surface layer on a semiconductor substrate having a doping level that is less than a doping level of the semiconductor substrate. A plurality of trenches are formed through at least one half of a thickness of the epitaxial semiconductor surface layer. The epitaxial semiconductor surface layer is thicker than a depth of the plurality of trenches. At least one capacitor dielectric layer lines a surface of the trenches. At least one trench fill layer on the dielectric layer fills the trenches.

公开(公告)号：US09825138B2

公开(公告)日：2017-11-21

申请号：US15188188

申请日：2016-06-21

Applicant: Texas Instruments Incorporated

Inventor： Hong Yang ,  Zachary K. Lee ,  Yufei Xiong ,  Yunlong Liu ,  Wei Tang

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/407 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/7834

Abstract: A method of fabricating a FET includes forming a gate on the surface of a substrate. A trench contact extends between a first region located proximate the surface of the substrate and a second region located below the first region is formed in the surface. The surface of the substrate is coated with a conductive material, wherein the conductive material at least partially covers the gate and lines the trench contact to electrically connect the first region and the second region. A void remains in the trench contact. A dielectric material is applied to the conductive material, wherein the dielectric material at least partially fills the void in the trench contact. At least a portion of the conductive material is etched from the gate.

公开(公告)号：US09397180B1

公开(公告)日：2016-07-19

申请号：US14695290

申请日：2015-04-24

Applicant: Texas Instruments Incorporated

Inventor： Hong Yang ,  Seetharaman Sridhar ,  Yufei Xiong ,  Yunlong Liu ,  Zachary K. Lee ,  Peng Hu

IPC: H01L21/00 ,  H01L29/45 ,  H01L29/417 ,  H01L29/78 ,  H01L29/732 ,  H01L29/739 ,  H01L21/311 ,  H01L21/768 ,  H01L21/288 ,  H01L21/3215 ,  H01L21/265

CPC classification number: H01L29/41766 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/743 ,  H01L23/485 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/456 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835

Abstract: An semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material. A method for forming a semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material.

Abstract translation: 一种具有低电阻沉降接触的半导体器件，其中低电阻沉降片接触被蚀刻穿过第一掺杂层并被蚀刻到第二掺杂层中，并且其中第一掺杂层覆盖在第二掺杂层上，并且其中第二掺杂层更重 掺杂了第一掺杂层，并且其中低电阻沉降片接触体填充有金属材料。 一种用于形成具有低电阻沉降接触的半导体器件的方法，其中所述低电阻沉降片接触被蚀刻通过第一掺杂层并且被蚀刻到第二掺杂层中，并且其中所述第一掺杂层覆盖所述第二掺杂层，并且其中所述第二掺杂 所述第一掺杂层更加重掺杂，并且其中所述低电阻沉降片接触体填充有金属材料。

公开(公告)号：US20160126193A1

公开(公告)日：2016-05-05

申请号：US14531177

申请日：2014-11-03

Applicant: Texas Instruments Incorporated

Inventor： Yunlong Liu ,  Yufei Xiong ,  Hong Yang

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/02 ,  H01L21/321 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L23/53295 ,  H01L21/31111 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In an semiconductor process, a seamless tungsten plug is formed in an inter-layer dielectric by forming the inter-layer dielectric from multiple oxide layers having different wet etch rates, from lowest wet-etch rate for the lowest layer to highest wet-etch rate for the highest layer, forming a hole or trench in the inter-layer dielectric using a dry etch process, reconfiguring the hole or trench to have sloped side walls by performing a wet etch step, and filling the hole or trench with tungsten and etching back the tungsten to form a seamless tungsten plug.

Abstract translation: 在半导体工艺中，通过从具有不同湿蚀刻速率的多个氧化物层形成层间电介质，从最低层的最低湿蚀刻速率到最高湿蚀刻速率，在层间电介质中形成无缝钨插塞 对于最高层，使用干蚀刻工艺在层间电介质中形成孔或沟槽，通过执行湿蚀刻步骤来重新配置孔或沟槽以具有倾斜的侧壁，并用钨填充孔或沟槽并蚀刻回 钨形成无缝钨丝塞。

公开(公告)号：US12080755B2

公开(公告)日：2024-09-03

申请号：US17512484

申请日：2021-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Furen Lin ,  Yunlong Liu ,  Zhi Peng Feng ,  Rui Liu ,  Rui Song ,  Manoj K Jain

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/495 ,  H01L27/08 ,  H01L29/66 ,  H01L49/02

CPC classification number: H01L28/91 ,  H01L28/92

Abstract: In a described example, a method of forming a capacitor includes forming a doped polysilicon layer over a semiconductor substrate. The method also includes forming a dielectric layer on the doped polysilicon layer. The method also includes forming an undoped polysilicon layer on the dielectric layer.

公开(公告)号：US11417736B2

公开(公告)日：2022-08-16

申请号：US17167911

申请日：2021-02-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Peng Li ,  Ya ping Chen ,  Yunlong Liu ,  Hong Yang ,  Shengpin Yang ,  Jing Hu ,  Chao Zhuang

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

Abstract: A method (200) of fabricating a semiconductor device includes etching (205) a group of trenches in a semiconductor surface layer of a substrate. The group of trenches includes an outermost trench that has a first width and remaining trenches of the group of trenches have a second width that is less than the first width. The outermost trench is formed at an edge of the group of trenches. A dielectric liner is formed (210) in the group of trenches and the dielectric liner is etched (215) in an upper portion of the group of trenches to remove a partial thickness of the dielectric liner. A full thickness of the dielectric liner is maintained in a lower portion of the group of trenches. The group of trenches is filled (220) with a polysilicon layer.